參數(shù)資料
型號(hào)： NS32FX16-25
廠(chǎng)商： National Semiconductor Corporation
英文描述： Imaging/Signal Processor
中文描述： 影像/信號(hào)處理器
文件頁(yè)數(shù)： 79/88頁(yè)
文件大小： 902K
代理商： NS32FX16-25
Appendix B: Instruction Execution Times
TOPiD If operand is in a register or is immediate then
TOPi
e
0
else if i
e
byte then TOPi
e
TOPB
else if i
e
word then TOPi
e
TOPW
else (i
e
double-word) then TOPi
e
TOPD
LD If i (operation length)
e
byte then L
e
1
else if i
e
word then L
e
2
else (i
e
double-word) L
e
4
fD If standard floating (32 bits): f
e
1
If long floating (64 bits): f
e
2
TfD Tf
e
4
TiD If integer
e
byte or word, then Ti
e
2
If integer
e
double-word, then Ti
e
4
B.1.2 Notes on Table Use
Values in the
Y
TEA1 and
Y
TEA2 columns indicate whether
effective addresses need to be calculated.
A value of 1 indicates that address calculation time is re-
quired for the corresponding operand. A 0 indicates that the
operand is either missing, or it is in a register and the in-
struction has an optimized form which eliminates the TEA
calculation for it.
In the L column, multiply the entry by the operation length in
bytes (1, 2 or 4).
In the TCY column, special notations sometimes appear:
n1
x
n2 means n1 minimum, n2 maximum
n1%n2 means that the instruction flushes the instruction
queue after n1 clock cycles and nonsequentially fetches the
next instruction. The value n2 indicates the number of clock
cycles for the internal execution of the instruction (including
n1).
The effective number of cycles (TCY) must take into ac-
count the time (T
fetch
) required to fetch the portion of the
next instruction including the basic encoding and the index
bytes. This time depends on the size and the alignment of
this portion.
If only one memory cycle is required, then:
TCY
e
n1
a
6
a
T
fetch
If more than one memory cycle is required, then:
TCY
e
n1
a
5
a
T
fetch
In the notes column, notations held within angle brackets
k l
indicate alternatives in the operand addressing modes
which affect the execution time. A table entry which is af-
fected by the operand addressing may have multiple values,
corresponding to the alternatives. These addressing nota-
tions are:
k
I
l
Immediate
k
R
l
CPU Register
k
M
l
Memory
k
F
l
FPU Register, either 32 or 64 Bits
k
x
l
Any Addressing Mode
k
ab
l
a and b represent the addressing modes of operand
1 and 2 respectively. Both a and b can be any ad-
dressing mode (e.g.,
k
MR
l
means memory to CPU
register).
Note:
Unless otherwise specified the TCY value for immediate addressing is
the same as for CPU register addressing.
B.1.3. Calculation of the Execution Time TEX for Basic
Instructions
The execution time for a basic instruction is obtained by
performing the following steps:
1. Find the desired instruction in Table B-1.
2. Calculate the values of TEA, TOPB, etc. using the num-
bers in the table and the equations given in the previous
sections.
3. The result derived by adding together these values is the
execution time TEX in clock cycles.
EXAMPLE
Calculate TEX for the instruction CMPW R0, TOS.
Operand 1 is in a register; Operand 2 is in memory. This
means that we must use the table values corresponding to
the
k
xM
l
case as given in the Notes column.
Only the
Y
TEA1,
Y
TEA2,
Y
TOPi and TCY columns have
values assigned for the CMPi instruction. Therefore, they
are they only ones that need to be calculated to find TEX.
The blank columns are irrelevant to this instruction.
Both
Y
TEA1 and
Y
TEA2 columns contain 1 for the
k
xM
l
case. This means that effective address times have to be
calculated for both operands. (For the
k
MR
l
case, the
Register operand would have required no TEA time, there-
fore only the Memory operand TEA would have been neces-
sary.) From the equations:
TEA1 (Register mode)
e
2.
TEA2 (Top of Stack mode, access class read)
e
2.
The
Y
TOPi column represents potential operand transfers
to or from memory. For a Compare instruction, each oper-
and is read once, for a total of two operand transfers.
TOPi (Word, Register)
e
0,
TOPi (Word, TOS)
e
3 (assuming the operand aligned)
Total TOPi
e
3
TCY is the time required for internal operation within the
CPU. The TCY value for this case is 3.
TEX
e
TEA1
a
TEA2
a
TOPi
a
TCY
e
2
a
2
a
3
a
3
e
10 machine cycles.
If the CPU is running at 20 MHz then a machine cycle (clock
cycle) is 50 ns. Therefore, this instruction would take 10
c
50 ns, or 0.5
m
s, to execute.
B.1.4 Calculation of the Execution Time TEX for Float-
ing-Point Instructions
The execution time for a floating-point instruction is ob-
tained by performing the following steps:
1. Find the desired instruction in Table B-2.
2. Calculate the values of TEA1, TEA2, TOPB, etc., using
the numbers in the table, and the equations given in the
previous sections.
3. Get the floating-point instruction execution time TFPU
from the appropriate FPU data sheet.
4. Choose the higher value between TPR and TFPU
a
3.
5. The result derived by adding together these values is the
execution time TEX in clock cycles.
EXAMPLE 1
Calculate TEX for the instruction MOVLF F0,
@
h
ê
3000.
Assumptions:
#
The FPU being used is the NS32181.
#
Write cycles are performed with no wait states.
79
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