參數(shù)資料
型號(hào)： NS32FX16-25
廠商： National Semiconductor Corporation
英文描述： Imaging/Signal Processor
中文描述： 影像/信號(hào)處理器
文件頁(yè)數(shù)： 51/88頁(yè)
文件大?。?/td> 902K
代理商： NS32FX16-25
3.0 Functional Description
(Continued)
Write cycle, the CPU applies data and activates SPC at T1,
removing SPC at T4. The Slave Processor latches the
status on the leading edge of SPC and latches data on the
trailing edge.
The CPU does not pulse the Address Strobe (ADS), and no
bus signals are generated. The direction of a transfer is de-
termined by the sequence (‘‘protocol’’) established by the
instruction under execution; but the CPU indicates the direc-
tion on the DDIN pin for hardware debugging purposes.
A Slave Processor operand is transferred in one or more
Slave bus cycles. A Byte operand is transferred on the
least-significant byte of the Data Bus (AD0–AD7), and a
Word operand is transferred on the entire bus. A Double
Word is transferred in a consecutive pair of bus cycles,
least-significant word first. A Quad Word is transferred in
two pairs of Slave cycles, with other bus cycles possibly
occurring between them. The word order is from least-signif-
icant word to most-significant.
Figure 3-27 shows the NS32FX16 and FPU connection dia-
gram.
TL/EE/10818–34
Note:
CPU samples Data Bus here.
FIGURE 3-25. Slave Processor Read Cycle
TL/EE/10818–35
*
Note:
Slave Processor samples Data Bus here.
FIGURE 3-26. Slave Processor Write Cycle
3.5.5.8 Data Access Sequences
The 24-bit address provided by the NS32FX16 is a byte
address; that is, it uniquely identifies one of up to
16,777,216 8-bit memory locations. An important feature of
the NS32FX16 is that the presence of a 16-bit data bus
imposes no restrictions on data alignment; any data item,
regardless of size, may be placed starting at any memory
address. The NS32FX16 provides a special control signal,
High Byte Enable (HBE), which facilitates individual byte ad-
dressing on a 16-bit bus.
Memory is organized as two 8-bit banks, each bank receiv-
ing the word address (A1–A23) in parallel. One bank, con-
nected to Data Bus pins AD0–AD7, is enabled to respond
to even byte addresses; i.e., when the least significant ad-
dress bit (A0) is low. The other bank, connected to Data Bus
pins AD8–AD15, is enabled when HBE is low. See Figure
3-28.
Any bus cycle falls into one of three categories: Even Byte
Access, Odd Byte Access, and Even Word Access. All ac-
cesses to any data type are made up of sequences of these
cycles. Table 3-7 gives the state of A0 and HBE for each
category.
51
相關(guān)PDF資料
PDF描述
NS32FX164-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FV16-25 Advanced Imaging/Communication Signal Processors
NS32FX164-25 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX161-15 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX161-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32FX164 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:
NS32FX164-20 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
NS32FX164-25 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
NS32FX164AV-25 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類(lèi)型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類(lèi)型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤(pán)
NS32FX164V-15 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
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