- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363665 > NS32FX16-25 (National Semiconductor Corporation) Imaging/Signal Processor PDF資料下載
參數(shù)資料
| 型號： | NS32FX16-25 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Imaging/Signal Processor |
| 中文描述： | 影像/信號處理器 |
| 文件頁數(shù)： | 27/88頁 |
| 文件大?。?/td> | 902K |
| 代理商： | NS32FX16-25 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
3.0 Functional Description
(Continued)
The CPU next sends the Operation Word while applying
Status Code 1101 (Transfer Slave Operand, Section
3.5.5.1). Upon receiving it, the Slave Processor decodes it,
and at this point both the CPU and the Slave Processor are
aware of the number of operands to be transferred and their
sizes. The Operation Word is swapped on the Data Bus;
that is, bits 0–7 appear on pins AD8–AD15 and bits 8–15
appear on pins AD0–AD7.
Using the Address Mode fields within the Operation Word,
the CPU starts fetching operands and issuing them to the
Slave Processor. To do so, it references any Addressing
Mode extensions which may be appended to the Slave
Processor instruction. Since the CPU is solely responsible
for memory accesses, these extensions are not sent to the
Slave Processor. The Status Code applied is 1101 (Transfer
Slave Processor Operand, Section 3.5.5.1).
After the CPU has issued the last operand, the Slave Proc-
essor starts the actual execution of the instruction. Upon
completion, it will signal the CPU by pulsing SPC low.
While the Slave Processor is executing the instruction, the
CPU is free to prefetch instructions into its queue. If it fills
the queue before the Slave Processor finishes, the CPU will
wait, applying Status Code 0011 (Waiting for Slave).
Upon receiving the pulse on SPC, the CPU uses SPC to
read a Status Word from the Slave Processor, applying
Status Code 1110 (Read Slave Status). This word has the
format shown inFigure 3-3. If the Q-bit (‘‘Quit’’, Bit 0) is set,
this indicates that an error was detected by the Slave Proc-
essor. The CPU will not continue the protocol, but will imme-
Status Combinations:
Send ID (ID): Code 1111
Xfer Operand (OP): Code 1101
Read Status (ST): Code 1110
Step
1
2
3
4
Status
ID
OP
OP
D
Action
CPU Sends ID Byte
CPU Sends Operation Word
CPU Sends Required Operands
Slave Starts Execution.
CPU Pre-Fetches.
Slave Pulses SPC Low
CPU Reads Status Word.
(Trap Alter Flags)
CPU Reads Results (If Any).
5
6
D
ST
7
OP
FIGURE 3-2. Slave Processor Protocol
diately trap through the Slave vector in the Interrupt Table.
Certain Slave Processor instructions cause CPU PSR bits to
be loaded from the Status Word.
The last step in the protocol is for the CPU to read a result,
if any, and transfer it to the destination. The Read cycles
from the Slave Processor are performed by the CPU while
applying Status Code 1101 (Transfer Slave Operand).
3.1.3.2 Floating-Point Instructions
Table 3-1 gives the protocols followed for each Floating-
Point instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
Appendix A.
TABLE 3-1. Floating-Point Instruction Protocols
Operand 2
Operand 1
Class
Issued
rmw.f
f
rmw.f
f
rmw.f
f
rmw.f
f
Mnemonic
Operand 1
Class
read.f
read.f
read.f
read.f
Operand 2
Issued
f
f
f
f
Returned Value
Type and Dest.
f to Op.2
f to Op.2
f to Op.2
f to Op.2
PSR Bits
Affected
none
none
none
none
ADDf
SUBf
MULf
DIVf
MOVf
ABSf
NEGf
read.f
read.f
read.f
write.f
write.f
write.f
f
f
f
N/A
N/A
N/A
f to Op.2
f to Op.2
f to Op.2
none
none
none
CMPf
read.f
read.f
f
f
N/A
N,Z,L
FLOORfi
TRUNCfi
ROUNDfi
read.f
read.f
read.f
write.i
write.i
write.i
f
f
f
N/A
N/A
N/A
i to Op.2
i to Op.2
i to Op.2
none
none
none
MOVFL
MOVLF
read.F
read.L
write.L
write.F
F
L
N/A
N/A
L to Op.2
F to Op.2
none
none
MOVif
read.i
write.f
i
N/A
f to Op.2
none
LFSR
SFSR
read.D
N/A
N/A
write.D
D
N/A
N/A
N/A
none
none
N/A
D to Op. 2
POLYf
DOTf
SCALBf
LOGBf
read.f
read.f
read.f
read.f
read.f
read.f
rmw.f
write.f
f
f
f
f
f
f
f
f to F0
f to F0
f to Op. 2
f to Op. 2
none
none
none
none
N/A
Notes:
D
e
Double Word
i
e
Integer size (B, W, D) specified in mnemonic.
f
e
Floating-Point type (F, L) specified in mnemonic.
N/A
e
Not Applicable to this instruction.
27
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NS32FX164-20 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FV16-25 | Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FX161-15 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FX161-20 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NS32FX164 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32FX164-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164AV-25 | 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| NS32FX164V-15 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。