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| 型號： | NS32FX16-25 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Imaging/Signal Processor |
| 中文描述： | 影像/信號處理器 |
| 文件頁數(shù)： | 20/88頁 |
| 文件大小： | 902K |
| 代理商： | NS32FX16-25 |
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2.0 Architectural Description
(Continued)
2.5.2.1 Frame Buffer Architecture
There are two basic types of frame buffer architectures:
plane-oriented or pixel-oriented. BITBLT takes advantage of
the plane-oriented frame buffer architecture’s attribute of
multiple, adjacent pixels-per-word, facilitating the movement
of large blocks of data. The source and destination starting
addresses are expressed as pixel addresses. The width and
height of the block to be moved are expressed in terms of
pixels and scan lines. The source block may start and end
at any bit position of any word, and the same applies for the
destination block.
2.5.2.2 Bit Alignment
Before a logical operation can be performed between the
source and the destination data, the source data must first
be bit aligned to the destination data. In Figure 2-15, the
source data needs to be shifted three bits to the right in
order to align the first pixel (i.e., the pixel at the top left
corner) in the source data block to the first pixel in the desti-
nation data block.
2.5.2.3 Block Boundaries and Destination Masks
Each BITBLT destination scan line may start and end at any
bit position in any data word. The neighboring bits (bits shar-
ing the same word address with any words in the destination
data block, but not a part of the BITBLT rectangle) of the
BITBLT destination scan line must remain unchanged after
the BITBLT operation.
Due to the plane-oriented frame buffer architecture, all
memory operations must be word-aligned. In order to pre-
serve the neighboring bits surrounding the BITBLT destina-
tion block, both a left mask and a right mask are needed for
all the leftmost and all the rightmost data words of the desti-
nation block. The left mask and the right mask both remain
the same during a BITBLT operation.
The following example illustrates the bit alignment require-
ments. In this example, the memory data path is 16 bits
wide. Figure 2-15 shows a 32 pixel by 32 scan line frame
buffer which is organized as a long bit stream which wraps
around every two words (32 bits). The origin (top left corner)
of the frame buffer starts from the lowest word in memory
(word address 00 (hex)).
Each word in the memory contains 16 bits, D0–D15. The
least significant bit of a memory word, D0, is defined as the
first displayed pixel in a word. In this example, BITBLT ad-
dresses are expressed as pixel addresses relative to the
origin of the frame buffer. The source block starting address
is 021 (hex) (the second pixel in the third word). The desti-
nation block starting address is 204 (hex) (the fifth pixel in
the 33rd word). The block width is 13 (hex), and the height is
06 (hex) (corresponding to 6 scan lines). The shift value is 3.
TL/EE/10818–6
FIGURE 2-15. 32-Pixel by 32-Scan Line Frame Buffer
20
相關PDF資料 |
PDF描述 |
|---|---|
| NS32FX164-20 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FV16-25 | Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FX161-15 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FX161-20 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| NS32FX164 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32FX164-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164AV-25 | 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| NS32FX164V-15 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
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