參數(shù)資料
型號(hào)： NS32FX16-25
廠商： National Semiconductor Corporation
英文描述： Imaging/Signal Processor
中文描述： 影像/信號(hào)處理器
文件頁(yè)數(shù)： 37/88頁(yè)
文件大小： 902K
代理商： NS32FX16-25
3.0 Functional Description
(Continued)
TABLE 3-2. Summary of Exception Processing
Exception
Instruction
Ending
Cleared before
Saving PSR
Cleared after
Saving PSR
Interrupt
Before Instruction
None /P
*
TUSPI
UND
SLAVE, SVC, DVZ, FLG, BPT, ILL
TRC
Suspended
Suspended
Before Instruction
P
TUS
TUSP
TUS
None
P
3.3 DEBUGGING SUPPORT
The NS32FX16 provides features to assist in program de-
bugging.
Besides the Breakpoint (BPT) instruction that can be used
to generate soft breaks, the CPU also provides the instruc-
tion tracing capability.
3.3.1 Instruction Tracing
Instruction tracing is a very useful feature that can be used
during debugging to single-step through selected portions of
a program. Tracing is enabled by setting the T-bit in the PSR
Register. When enabled, the CPU generates a Trace Trap
(TRC) after the execution of each instruction.
At the beginning of each instruction, the T-bit is copied into
the PSR P (Trace ‘‘Pending’’) bit. If the P-bit is set at the end
of an instruction, then the Trace Trap is activated. If any
other trap or interrupt request is made during a traced in-
struction, its entire service procedure is allowed to complete
before the Trace Trap occurs. Each interrupt and trap se-
quence handles the P-bit for proper tracing, guaranteeing
only one Trace Trap per instruction, and guaranteeing that
the Return Address pushed during a Trace Trap is always
the address of the next instruction to be traced.
The beginning of the execution of a TRAP(UND) is not con-
sidered to be a beginning of an instruction, and hence the
T-bit is not copied into the P-bit.
Due to the fact that some instructions can clear the T- and
P-bits in the PSR, in some cases a Trace Trap may not
occur at the end of the instruction. This happens when one
of the privileged instructions BICPSRW or LPRW PSR is
executed.
In other cases, it is still possible to guarantee that a Trace
Trap occurs at the end of the instruction, provided that spe-
cial care is taken before returning from the Trace Trap Serv-
ice Procedure. In case a BICPSRB instruction has been ex-
ecuted, the service procedure should make sure that the
T-bit in the PSR copy saved on the Interrupt Stack is set
before executing the RETT instruction to return to the pro-
gram being traced. If the RETT or RETI instructions have to
be traced, the Trace Trap Service Procedure should set the
P- and T-bits in the PSR copy on the Interrupt Stack that is
going to be restored in the execution of such instructions.
While debugging the NS32FX16 instructions which have in-
terior loops (BBOR, BBXOR, BBAND, BBFOR, EXTBLT,
MOVMP, SBITPS, TBITS), special care must be taken with
the single-step trap. If an interrupt occurs during a single-
step of one of the graphics instructions, the interrupt will be
serviced. Upon return from the interrupt service routine, the
new NS32FX16 instruction will not be re-entered, due to a
single-step trap. Both the NMI and INT interrupts will cause
this behavior. Another single-step operation (S command in
DBG16/MONCG) will resume from where the instruction
was interrupted. There are no side effects from this early
termination, and the instruction will complete normally.
For all other Series 32000 instructions, a single-step opera-
tion will complete the entire instruction before traping back
to the debugger. On the instructions mentioned above, serv-
eral single-step commands may be required to complete the
instruction, ONLY when interrupts are occurring.
There are some methods to give the appearance of single-
stepping for these NS32FX16 instructions.
1. MON16/MONCG monitors the return from single-step
trap vector, PC value. If the PC has not changed since
the last single-step command was issued, the single-step
operation is repeated. It is also advisable to ensure that
one of the NS32FX16 instructions is being single-
stepped, by inspecting the first byte of the address point-
ed to by the PC register. If it is 0x0E, then the instruction
is an NS32FX16-specific instruction.
2. A breakpoint following the instruction would also trap af-
ter the instruction had completed.
Note:
If instruction tracing is enabled while the WAIT instructioin is execut-
ed, the Trap (TRC) occurs after the next interrupt, when the interrupt
service procedure has returned.
3.4 DSP MODULE (DSPM)
The DSP Module is specifically designed to execute high-
speed vector operations on complex numbers. This is espe-
cially needed to meet the performance requirements in mo-
dem applications as well as to efficiently implement digital
filters and other DSP primitives.
Detailed descriptions of the operational characteristics are
provided in the following sections.
3.4.1 DSPM Operation
A block diagram of the DSP Module including the RAM array
is shown in Figure 3-12. In order to maximize performance,
an internal two-stage pipeline is provided. This allows to
overlap operand fetches and multiply-accumulate opera-
tions for different vector elements.
Two data elements at a time can be fetched: one from main
memory and the other from the on-chip RAM Array.
While fetching operands for one vector element, the DSPM
performs the multiplication and additions on the previous
vector element. Each complex multiply and accumulate op-
eration requires two operand fetches, four multiplications
and four additions. The DSPM pipeline allows a maximal
throughput of a complex multiply accumulate operation in 8
clock cycles.
The DSPM uses the full bandwidth of the external bus dur-
ing VCMAD, VCMUL or VCMAC operations. See Section
3.4.3.
While executing the VCMAG instruction, the external bus is
free as no external operands are required. In this case the
CPU can execute instructions in parallel with the DSPM.
37
相關(guān)PDF資料
PDF描述
NS32FX164-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FV16-25 Advanced Imaging/Communication Signal Processors
NS32FX164-25 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX161-15 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX161-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32FX164 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
NS32FX164-20 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
NS32FX164-25 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
NS32FX164AV-25 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤
NS32FX164V-15 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
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