參數(shù)資料
型號(hào)： NS32FX16-25
廠商： National Semiconductor Corporation
英文描述： Imaging/Signal Processor
中文描述： 影像/信號(hào)處理器
文件頁(yè)數(shù)： 19/88頁(yè)
文件大小： 902K
代理商： NS32FX16-25
2.0 Architectural Description
(Continued)
2.5 GRAPHICS SUPPORT
The following sections provide a brief description of the
NS32FX16 graphics support capabilities. Basic discussions
on frame buffer addressing and BITBLT operations are also
provided. More detailed information on the NS32FX16
graphics
support
instructions
NS32CG16 Printer/Display Processor Programmer’s Refer-
ence.
can
be
found
in
the
2.5.1 Frame Buffer Addressing
There are two basic addressing schemes for referencing
pixels within the frame buffer: Linear and Cartesian (or x-y).
Linear addressing associates a single number to each pixel
representing the physical address of the corresponding bit
in memory. Cartesian addressing associates two numbers
to each pixel representing the x and y coordinates of the
pixel relative to a point in the Cartesian space taken as the
origin. The Cartesian space is generally defined as having
the origin in the upper left. A movement to the right increas-
es the x coordinate; a movement downward increases the y
coordinate.
The correspondence between the location of a pixel in the
Cartesian space and the physical (BIT) address in memory
is shown in Figure 2-14. The origin of the Cartesian space
(x
e
0, y
e
0) corresponds to the bit address ‘ORG’. Incre-
menting the x coordinate increments the bit address by one.
Incrementing the y coordinate increments the bit address by
an amount representing the warp (or pitch) of the Cartesian
space. Thus, the linear address of a pixel at location (x, y) in
the Cartesian space can be found by the following expres-
sion.
ADDR
e
ORG
a
y
*
WARP
a
x
Warp is the distance (in bits) in the physical memory space
between two vertically adjacent bits in the Cartesian space.
Example 1 below shows two NS32FX16 instruction se-
quences to set a single pixel given the x and y coordinates.
Example 2 shows how to create a fat pixel by setting four
adjacent bits in the Cartesian space.
Example 1:
Set pixel at location (x, y)
Setup:
R0 x coordinate
R1 y coordinate
Instruction Sequence 1:
MULD
WARP, R1
; Y*WARP
ADDD
R0, R1
;
0
X
4
BIT OFFSET
SBITD
R1, ORG
; SET PIXEL
Instruction Sequence 2:
INDEXD R1, (WARP-1), R0
; Y*WARP
0
X
SBITD
R1, ORG
; SET PIXEL
Example 2:
Create fat pixel by setting bits at locations
(x, y), (x
a
1, y), (x, y
a
1) and (x
a
1, y
a
1).
Setup:
R0 x coordinate
R1 y coordinate
Instruction Sequence:
INDEXD
R1, (WARP-1), R0
; BIT ADDRESS
SBITD
41, ORG
; SET FIRST PIXEL
ADDQD
1, R1
; (X
0
1, Y)
SBITD
R1, ORG
; SECOND PIXEL
ADDD
(WARP-1), R1
; (X, Y
0
1)
SBITD
R1, ORG
; THIRD PIXEL
ADDQD
1, R1
; (X
0
1, Y
0
1)
SBITD
R1, ORG
; LAST PIXEL
TL/EE/10818–5
FIGURE 2-14. Correspondence between
Linear and Cartesian Addressing
2.5.2 BITBLT Fundamentals
BITBLT, BIT-aligned BLock Transfer, is a general operator
that provides a mechanism to move an arbitrary size rectan-
gle of an image from one part of the frame buffer to another.
During the data transfer process a bitwise logical operation
can be performed between the source and the destination
data. BITBLT is also called RasterOp: operations on rasters.
It defines two rectangular areas, source and destination,
and performs a logical operation (e.g., AND, OR, XOR) be-
tween these two areas and stores the result back to the
destination. It can be expressed in simple notation as:
Source op Destination
x
Destination
op: AND, OR, XOR, etc.
19
相關(guān)PDF資料
PDF描述
NS32FX164-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FV16-25 Advanced Imaging/Communication Signal Processors
NS32FX164-25 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX161-15 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FX161-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32FX164 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:
NS32FX164-20 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
NS32FX164-25 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
NS32FX164AV-25 功能描述:IC IMAGING COMM SGNL PROC PLCC68 RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類(lèi)型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類(lèi)型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤(pán)
NS32FX164V-15 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
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