參數(shù)資料
型號: NAND04GA3C2AN1E
廠商: 意法半導體
英文描述: 4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
中文描述: 4Gbit的,2112字節(jié)的頁,3V供電,多級NAND閃存
文件頁數(shù): 17/51頁
文件大小: 374K
代理商: NAND04GA3C2AN1E
NAND04GA3C2A, NAND04GW3C2A
5 Command Set
17/51
5
Command Set
All bus write operations to the device are interpreted by the Command Interface. The
Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is high. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The Commands are summarized in
Table 8: Commands
.
Commands
Table 8.
Command
Bus Write Operations
(1)
Commands
accepted
during busy
1
st
CYCLE
2
nd
CYCLE
3
rd
CYCLE
4
th
CYCLE
Read
00h
(2)
30h
Random Data Output
05h
E0h
Cache Read
00h
31h
Exit Cache Read
34h
Yes
(3)
Page Program
(Sequential Input default)
80h
10h
Random Data Input
85h
Block Erase
60h
D0h
Reset
FFh
Yes
Read Electronic Signature
90h
Read Status Register
70h
Yes
1.
The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are
not shown.
2.
For consecutive read operations the 00h command does not need to be repeated.
3.
Only when a Cache Read operation is ongoing.
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