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| 型號(hào)： | MX98905BFC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| 中文描述： | 該MX98905是專(zhuān)為易于實(shí)現(xiàn)的多址/光盤(pán)局域網(wǎng)， |
| 文件頁(yè)數(shù)： | 68/86頁(yè) |
| 文件大?。?/td> | 352K |
| 代理商： | MX98905BFC |
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68
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
Bit assignment
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TPSR
A15
A14
A13
A12
A11
A10
A9
A8
(A7-A0 initialized to zero)
16. DMA REGISTERS (Continued)
TRANSMIT DMA REGISTER (TPSR)
This register points to the page where the assembled
packet is ready to be transmitted. Only the eight higher
order addresses are specified since all transmit packets
are assembled on 256-byte page boundaries. The bit
TRANSMIT BYTE COUNT REGISTER 0, 1 (TBCR0, 1)
These two registers indicate the length of the packet to be
transmitted in bytes. The count must include the number
of bytes in the source, destination, length and data fields
(CRC field is exclusive). The maximum number of trans-
mit bytes allowed is 64 kbytes. The ENC will not truncate
transmissions whenever packet length is longer than
1500 bytes. Hence, in order to meet the IEEE 802.3
standard, software driver on upper layer must take care of
maximum length problem by itself. The bit assignment is
shown below:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBCR1
L15
L14
L13
L12
L11
L10
L9
L8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBCR0
L7
L6
L5
L4
L3
L2
L1
L0
assignment is shown below. The values placed in bits D7-
D0 will be used to initialize the higher order address (A15-
A8) of the Local DMA for transmission while the lower
order bits (A7-A0) are initialized to zero.
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