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參數(shù)資料
| 型號： | MX98905BFC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The MX98905 is designed for easy implementation of CSMA/CD local area networks, |
| 中文描述： | 該MX98905是專為易于實現(xiàn)的多址/光盤局域網(wǎng)， |
| 文件頁數(shù)： | 43/86頁 |
| 文件大?。?/td> | 352K |
| 代理商： | MX98905BFC |
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43
P/N: PM0365
REV. 1.3, NOV 20 ,1995
MX98905B
31 CONFIGURATION REGISTER B (R/W) (CB) (Continued)
SYMBOL
BIT
DESCRIPTION
IO16CON
D3
IO16L CONTROL.
When this bit is set low, IO16L is generated only on address
decode. When it is high, the MX98905 will generate IO16L after IORDL, or IOWRL
go active.
CHANRD
D4
CHRDY FROM IORDL OR IOWRL OR FROM BALE.
When this bit is set low, the
MX98905 will generate CHRDY after the command strobe. When it is high, CHRDY
will be generated by the MX98905 after BALE goes high.
BE
D5
BUS ERROR.
This bit shows that the MX98905 has detected a bus error (the
MX98905 attempts to insert wait state into a system access and the system
terminates the cycle without monitoring the wait state). Writing a one to this bit clears
it to zero, but writing a zero to this bit has no effect.
BPWR
D6
BOOT PROM WRITE.
Write cycles will be generated to the boot PROM only when
this bit is set high.
EESTORE
D7
EEPROM STORE.
Writing a one to this bit enables the EEPROM STORE algorithm,
as mentioned. This bit should not be configured to high either from switches or from
an EEPROM. Note that this bit and IDWCMD of HCMR can't be set high simultane-
ously to prevent crashing the internal state machine of the MX98905.
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