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參數(shù)資料
| 型號： | MX29LV640BUTC-12G |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | DRAM |
| 英文描述： | 64M-BIT [4M x 16] CMOS EQUAL SECTOR FLASH MEMORY |
| 中文描述： | 4M X 16 FLASH 2.7V PROM, 120 ns, PDSO48 |
| 封裝： | 12 X 20 MM, ROHS COMPLIANT, MO-142, TSOP1-48 |
| 文件頁數(shù)： | 20/64頁 |
| 文件大?。?/td> | 509K |
| 代理商： | MX29LV640BUTC-12G |
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20
P/N:PM1081
REV. 1.0, MAR. 08, 2005
MX29LV640BU
This method is an alternative to that shown in Table 1,
which is intended for PROM programmers and requires
V
ID
on address bit A9.
The SILICON ID READ command sequence is initiated
by writing two unlock cycles, followed by the SILICON
ID READ command. The device then enters the SILICON
ID READ mode, and the system may read at any address
any number of times, without initiating another command
sequence. A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address XX01h
returns the device code. A read cycle containing a sector
address (SA) and the address 02h returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to
Table for valid sector addresses.
The system must write the reset command to exit the
Automatic Select
mode and return to reading array data.
WORD PROGRAM COMMAND SEQUENCE
The command sequence requires four bus cycles, and is
initiated by writing two unlock write cycles, followed by
the program set-up command. The program address and
data are written next, which in turn initiate the Embedded
Program algorithm. The system is
not
required to provide
further controls or timings. The device automatically
generates the program pulses and verifies the
programmed cell margin. Table 3 shows the address and
data requirements for the word program command
sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status of the program operation by using Q7, Q6, or RY/
BY#. See "Write Operation Status" for information on these
status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operation. The Word Program command sequence should
be reinitiated once the device has reset to reading array
data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the
operation and set Q5 to "1" ,
”
or cause the Data# Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0". Only erase operations can convert a "0" to a
"1".
SETUP AUTOMATIC CHIP/SECTOR ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H, or the
sector erase command 30H.
The MX29LV640BU contains a Silicon-ID-Read operation
to supplement traditional PROM programming methodol-
ogy. The operation is initiated by writing the read silicon
ID command sequence into the command register. Fol-
lowing the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 22D7H for MX29LV640BU.
AUTOMATIC
COMMAND
CHIP/SECTOR
ERASE
The device does not require the system to preprogram
prior to erase. The Automatic Erase algorithm automati-
cally pre-program and verifies the entire memory for an
all zero data pattern prior to electrical erase. The system
is not required to provide any controls or timings during
these operations. Table 3 shows the address and data
requirements for the chip erase command sequence.
Any commands written to the chip during the Automatic
Erase algorithm are ignored. Note that a hardware reset
during the chip erase operation immediately terminates
the operation. The Chip Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase opera-
tion by using Q7, Q6, Q2, or RY/BY#. See "Write Opera-
tion Status" for information on these status bits. When
the Automatic Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 5 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in "AC Char-
acteristics" for parameters, and to Figure 4 for timing
diagrams.
相關(guān)PDF資料 |
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| MX29LV640BUTC-90 | 64M-BIT [4M x 16] CMOS EQUAL SECTOR FLASH MEMORY |
| MX29LV640BUTC-90G | 64M-BIT [4M x 16] CMOS EQUAL SECTOR FLASH MEMORY |
| MX29LV640BUTI-12 | 64M-BIT [4M x 16] CMOS EQUAL SECTOR FLASH MEMORY |
| MX29LV640BUTI-12G | 64M-BIT [4M x 16] CMOS EQUAL SECTOR FLASH MEMORY |
| MX29LV640BUTI-90 | 64M-BIT [4M x 16] CMOS EQUAL SECTOR FLASH MEMORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX29LV640EBTI-70G | 功能描述:IC FLASH PAR 3V 64MB 70NS 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:MX29LV 標準包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| MX29LV640EBXEI-70G | 功能描述:IC FLASH PAR 64MB 70NS 48FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:MX29LV 標準包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| MX29LV640EBXEI-70GTR | 制造商:Macronix International Co Ltd 功能描述:MX29LV Series 3 V 64 Mb (8M x 8/4M x 16) 70 ns Parallel Flash - TFBGA-48 |
| MX29LV640EBXEI-90G | 制造商:Macronix International Co Ltd 功能描述:MX29LV Series 3 V 64 Mb (8M x 8/4M x 16) 90 ns Parallel Flash - TFBGA-48 |
| MX29LV640ETTI-70G | 功能描述:IC FLASH PAR 3V 64MB 70NS 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:MX29LV 標準包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
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