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| 型號(hào)： | MX28F640C3BTC-12 |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 64M-BIT [4M x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY |
| 中文描述： | 4M X 16 FLASH 3V PROM, 120 ns, PDSO48 |
| 封裝： | 12 X 20 MM, MO-142, TSOP1-48 |
| 文件頁(yè)數(shù)： | 20/44頁(yè) |
| 文件大?。?/td> | 653K |
| 代理商： | MX28F640C3BTC-12 |
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20
P/N:PM0900
MX28F640C3T/B
REV. 0.6, AUG. 20, 2003
5. 128-Bit Protection Register
The 128-bits of protection register are divided into two
64-bit segments. One of the segments is programmed
at MXIC side with unique 64-bit number; where changes
are forbidden. The other segment is left empty for cus-
tomer to program. Once the customer segment is pro-
grammed, it can be locked to prevent further reprogram-
ming.
5.1 Protection Register Read & Programming
The protection register is read in the configuration read
mode, which follows the stated Command Bus Defini-
tions.
The device is switched to this read mode by writing the
Read Configuration command (90H). Once this mode,
read cycles from addresses shown in Table 7 will re-
trieve the specified information. To return to read array
mode, write the Read Array Command (FFH).
Two-cycle Protection Program Command is used to pro-
gram protection register bits. The 64-bit register is pro-
grammed 16-bits at a time. First write C0H protection
program setup. The next write to the device will latch in
address and data and program the specified location.
The allowable address are also show in Table 7. Refer to
Figure 6 for the Protection Register Programming Flow-
chart.
Any attempt to address Protection Program command
onto undefined protection register address space will
result in a Status Register error (SR.4 set to "1"). In
addition, attempting to program or to previously locked
protection register segment will result in a status regis-
ter error (SR.4=1, SR.1=1).
Word
Lock
0
1
2
3
4
5
6
7
User
Both
Factory
Factory
Factory
Factory
Customer
Customer
Customer
Customer
A7
1
1
1
1
1
1
1
1
1
A6
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
A2
0
0
0
0
1
1
1
1
0
A1
0
0
1
1
0
0
1
1
0
A0
0
1
0
1
0
1
0
1
0
Table 7. Word-Wide Protection Register Addressing
5.2 Protection Register Locking
The user-programmable segment of the protection reg-
ister is lockable by programming Bit 1 of the PR-Lock
location to 0. Bit 0 of this location is programmed to 0 at
MXIC to protect the unique device number. This bit is
set using the unique device number. This bit is set using
the protection program command to program "FFFD" to
PR-LOCK location. After these bits have been pro-
grammed, no further changes can be made to the value
stored in the protection register. Protection program com-
mand to a locked section will result in a status register
error (Program Error bit SR.4 and Lock Error bit SR.1
will be set to 1). Protection register lockout state is not
reversible.
Protection Register
Bit Address
88H~85H
84H~81H
Purpose
4 word user program Register
4 word factory program
Register
Protection Register Lock
(PR-Lock)
80H(Bit0 & Bit1)
Table 8. Protection Register Memory Map
Notes: 1. Set address bit A21-A15=1 for TOP Boot device.
2. Set address bit A21-A15=0 for Bottom Boot device.
3. The address not specified in above are don't care.
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