參數(shù)資料
型號: MX28F640C3BTC-12
廠商: MACRONIX INTERNATIONAL CO LTD
元件分類: DRAM
英文描述: 64M-BIT [4M x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
中文描述: 4M X 16 FLASH 3V PROM, 120 ns, PDSO48
封裝: 12 X 20 MM, MO-142, TSOP1-48
文件頁數(shù): 14/44頁
文件大?。?/td> 653K
代理商: MX28F640C3BTC-12
14
P/N:PM0900
MX28F640C3T/B
REV. 0.6, AUG. 20, 2003
4.1 Read Array Command
Upon initial device power-up and after exit from reset
mode, the device defaults to read array mode. This op-
eration is also initiated by writing the Read Array com-
mand. The device remains enabled for reads until an-
other command is written. Once the internal WSM has
started a sector erase, word write or sector lock con-
figuration the device will not recognize the Read Array
command until the WSM completes its operation unless
the WSM is suspended via a Sector Erase Suspend or
Word Write Suspend command. If RESET=VIL device
is in read Read Array command mode, this read opera-
tion no longer requires VPP. The Read Array command
functions independently of the VPP voltage and RESET
can be VIH.
4.2 Read Configuration Codes Command
The configuration code operation is initiated by writing
the Read Configuration Codes command (90H). To re-
turn to read array mode, write the Read Array Command
(FFH). Following the command write, read cycles from
addresses shown in Table 4 retrieve the manufacturer,
device, sector lock configuration codes (see Table 4 for
configuration code values). To terminate the operation,
write another valid command. Like the Read Array com-
mand, the Read Configuration Codes command func-
tions independently of the VPP voltage and RESET can
be VIH. Following the Read Configuration Codes com-
mand, the information is shown:
Code
Address
Data
(A19-A0)
(Q15-Q0)
Manufacturer Code
00000H
00C2H
Device Code
00001H
88CC/88CDH
Sector Lock Configuration XX002H
LocK
- Sector is unlocked
Q0=0
- Sector is locked
Q0=1
- Sector is locked-down
Q1=1
Protection Register Lock
80
PR-LK
Protection Register
81-88
PR
Table 4: ID Code
4.3 Read Status Register Command
CUI writes read status command (70H). The status reg-
ister may be read to determine when a sector erase,
word write or lock-bit configuration is complete and
whether the operation completed successfully. (refer to
table 6) It may be read at any time by writing the Read
Status Register command. After writing this command,
all subsequent read operations output data from the sta-
tus register until another valid command is written. The
status register contents are latched on the falling edge
of CE or OE, whichever occurs. CE or OE must toggle
to VIH before further reads to update the status register
latch. The Read Status Register command functions in-
dependently of the VPP voltage. RESET can be VIH.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear
Status Register command (50H). These bits indicate
various failure conditions (see Table 6). By allowing sys-
tem software to reset these bits, several operations (such
as cumulatively erasing multiple sectors or writing sev-
eral words in sequence) may be performed. The status
register may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status Register
command (50H) is written on CUI. It functions indepen-
dently of the applied VPP Voltage. RESET can be VIH.
This command is not functional during sector erase or
word write suspend modes.
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