參數(shù)資料
型號: MVTX2604
廠商: Zarlink Semiconductor Inc.
英文描述: Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch
中文描述: 管理24端口的10/100 Mb 2端口千兆以太網(wǎng)交換機(jī)1
文件頁數(shù): 32/173頁
文件大?。?/td> 2097K
代理商: MVTX2604
MVTX2604
Data Sheet
34
Zarlink Semiconductor Inc.
Figure 10 - Memory Configuration For: 2 Banks, 1 Layer, 4 MB
6.0 Frame Engine
6.1 Data Forwarding Summary
When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB.
Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface.
A switch request is sent to the Search Engine. The Search Engine processes the switch request.
A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast and its
destination port or ports. A VLAN table lookup is performed as well.
A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a
Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling
Queue (TxSch Q) or Queues. There are 4 TxSch Q for each 10/100 port (and 8 per Gigabit port), one for each
priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast or adding
an entry to a physical queue if multicast.
When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of
the TxSch Qs, according to the transmission scheduling algorithm (to ensure per-class quality of service). The
unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The older
HOL between the two queues goes first. For 10/100 ports multicast queue 0 is associated with unicast queue 0 and
multicast queue 1 is associated with unicast queue 2. For Gigabit ports multicast queue 0 is associated with unicast
queue 0, multicast queue 1 with unicast queue 2, multicast queue 2 with unicast queue 4 and multicast queue 3
with unicast queue 6.
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the
destination port.
ZBT
Memory
256 K
32 bits
ZBT
Memory
256 K
32 bits
Data LA_D[63:32]
Data LA_D[31:0]
Address LA_A[20:3]
Bank A (2 M One Layer)
Bootstraps: TSTOUT7 = Pull Down, TSTOUT13 = Open, TSTOUT4 = Open
Memory
256 K
32 bits
ZBT
Memory
256 K
32 bits
Data LB_D[63:32]
Data LB_D[31:0]
Address LB_A[20:3]
Bank B (2 M One Layer)
ZBT
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