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參數(shù)資料
| 型號(hào)： | MVTX2604 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| 中文描述： | 管理24端口的10/100 Mb 2端口千兆以太網(wǎng)交換機(jī)1 |
| 文件頁(yè)數(shù)： | 103/173頁(yè) |
| 文件大?。?/td> | 2097K |
| 代理商： | MVTX2604 |
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MVTX2604
Data Sheet
105
Zarlink Semiconductor Inc.
Similarly, the User Defined Logical Port provides the user programmability to the priority, plus the flexibility to select
specific logical ports to fit the applications. The 8 User Logical Ports can be programmed via User_Port 0-7
registers. Two registers are required to be programmed for the logical port number. The respective priority can be
programmed to the User_Port [7:0] priority register. The port priority can be individually enabled/disabled via
User_Port_Enable register.
The User Defined Range provides a range of logical port numbers with the same priority level. Programming is
similar to the User Defined Logical Port. Instead of programming a fixed port number, an upper and lower limit need
to be programmed, they are: {RHIGHH, RHIGHL} and {RLOWH, RLOWL} respectively. If the value in the upper
limit is smaller or equal to the lower limit, the function is disabled. Any IP packet with a logical port that is less than
the upper limit and more than the lower limit will use the priority specified in RPRIORITY.
14.10.40.1 USER_PORT0_(0~7) – U
SER
D
EFINE
L
OGICAL
P
ORT
(0~7)
USER_PORT_0 - I
2
C Address h0D6 + 0DE; CPU Address 580(Low) + 581(high)
USER_PORT_1 - I
2
C Address h0D7 + 0DF; CPU Address 582 + 583
USER_PORT_2 - I
2
C Address h0D8 + 0E0; CPU Address 584 + 585
USER_PORT_3 - I
2
C Address h0D9 + 0E1; CPU Address 586 + 587
USER_PORT_4 - I
2
C Address h0DA + 0E2; CPU Address 588 + 589
USER_PORT_5 - I
2
C Address h0DB + 0E3; CPU Address 58A + 58B
USER_PORT_6 - I
2
C Address h0DC + 0E4; CPU Address 58C + 58D
USER_PORT_7 - I
2
C Address h0DD + 0E5; CPU Address 58E + 58F
Accessed by CPU, serial interface and I
2
C (R/W)
(Default 00) This register is duplicated eight times from PORT 0 through PORT 7 and allows the CPU to define
eight separate ports.
14.10.40.2 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority
I
2
C Address h0E6, CPU Address 590
Accessed by CPU, serial interface and I
2
C (R/W)
The chip allows the CPU to define the priority
7
0
TCP/UDP Logic Port Low
7
0
TCP/UDP Logic Port High
7
5
4
3
1
0
Priority 1
Drop
Priority 0
Drop
Bits [3:0]:
Priority setting, transmission + dropping, for logic port 0
Bits [7:4]:
Priority setting, transmission + dropping, for logic port 1 (Default 00)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MVTX2604AG | Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| MVTX2801 | Unmanaged 4-Port 1000 Mbps Ethernet Switch |
| MVTX2801AG | Unmanaged 4-Port 1000 Mbps Ethernet Switch |
| MVTX2802 | Managed 4-Port 1000 Mbps Ethernet Switch |
| MVTX2802AG | Managed 4-Port 1000 Mbps Ethernet Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MVTX2604A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MVTX260x Physical Port Control |
| MVTX2604AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| MVTX2801 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 4-Port 1000 Mbps Ethernet Switch |
| MVTX2801A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Unmanaged 4 port Gigabit Ethernet switch |
| MVTX2801AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Unmanaged 4-Port 1000 Mbps Ethernet Switch |
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