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參數(shù)資料
| 型號(hào)： | MVTX2604 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| 中文描述： | 管理24端口的10/100 Mb 2端口千兆以太網(wǎng)交換機(jī)1 |
| 文件頁(yè)數(shù)： | 22/173頁(yè) |
| 文件大小： | 2097K |
| 代理商： | MVTX2604 |
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MVTX2604
Data Sheet
24
Zarlink Semiconductor Inc.
Figure 4 - MVTX2604 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only)
4.2 ZBT Support
The MVTX2604 supports Zero Bus Turnaround (ZBT). ZBT is a synchronous SRAM architecture that is optimized
for networking and telecommunications applications. It can significantly increase the switch’s internal bandwidth
when compared to standard Pipeline SyncBurst SRAM.
The ZBT architecture is optimized for switching and other applications with highly random READs and WRITEs.
ZBT SRAMs eliminate all idle cycles when turning the data bus around from a WRITE operation to a READ
operation (or vice versa). This feature results in dramatic performance improvements in systems that have such
traffic patterns (that is, frequent and random read and write access to the SRAM).
Please refer to the ZBT Application Note for further details.
4.3 Detailed Memory Information
Because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from
memory. The first 8-byte granule gets written to Bank A, the second 8-byte granule gets written to Bank B and so on
in alternating fashion. When reading frames from memory, the same procedure is followed, first from A, then from B
and so on.
The reading and writing from alternating memory banks can be performed with minimal waste of memory
bandwidth. What’s the worst case For any speed port, in the worst case, a 1-byte-long EOF granule gets written
to Bank A. This means that a 7-byte segment of Bank A bandwidth is idle, and furthermore, the next 8-byte
segment of Bank B bandwidth is idle, because the first 8 bytes of the next frame will be written to Bank A, not B.
This scenario results in a maximum 15 bytes of waste per frame, which is always acceptable because the
interframe gap is 20 bytes.
The CPU management port gets treated like any other port, reading and writing to alternating memory banks
starting with Bank A. The VLAN Index Mapping Table and Mac Address Table are duplicated in Bank A and B.
When the CPU writes an entry to the VLAN Index Mapping Table it has to write the same data in bank A and bank
B. Search engine data is written to both banks in parallel. In this way, a search engine read operation can be
performed by either bank at any time without a problem.
SRAM
TX DMA
0-7
TX DMA
8-15
TX DMA
16-23
RX DMA
0-7
RX DMA
8-15
RX DMA
16-23
SRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MVTX2604AG | Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| MVTX2801 | Unmanaged 4-Port 1000 Mbps Ethernet Switch |
| MVTX2801AG | Unmanaged 4-Port 1000 Mbps Ethernet Switch |
| MVTX2802 | Managed 4-Port 1000 Mbps Ethernet Switch |
| MVTX2802AG | Managed 4-Port 1000 Mbps Ethernet Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MVTX2604A | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:MVTX260x Physical Port Control |
| MVTX2604AG | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Managed 24-Port 10/100 Mb + 2 Port 1 Gb Ethernet Switch |
| MVTX2801 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Unmanaged 4-Port 1000 Mbps Ethernet Switch |
| MVTX2801A | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Unmanaged 4 port Gigabit Ethernet switch |
| MVTX2801AG | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Unmanaged 4-Port 1000 Mbps Ethernet Switch |
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