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MVTX2604
Data Sheet
22
Zarlink Semiconductor Inc.
Cascade Stacking configuration. Up to 32 devices. Devices are connected to form a list configuration.
Devices are connected by two Gigabit links, except the two devices at both ends, where one Gigabit port is
used as an uplink port. Flow control may be enabled in this configuration.
3.0 MVTX2604 Data Forwarding Protocol
3.1 Unicast Data Frame Forwarding
When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An
FCB handle will always be available because of advance buffer reservations.
The memory (SRAM) interface consists of two 64-bit buses, connected to two SRAM banks, A and B. The Receive
DMA (RxDMA) is responsible for multiplexing the data and the address. On a port’s “turn,” the RxDMA will move 8
bytes (or up to the end-of-frame) from the port’s associated RxFIFO into memory (Frame Data Buffer, or FDB).
Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx
interface makes a switch request. The RxDMA arbitrates among multiple switch requests.
The switch request consists of the first 64 bytes of a frame, containing among other things, the source and
destination MAC addresses of the frame. The search engine places a switch response in the switch response
queue of the frame engine when done. Among other information, the search engine will have resolved the
destination port of the frame and will have determined that the frame is unicast.
After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is
responsible for notifying the destination port that it has a frame to forward to it. But first, the TxQ manager has to
decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy
at the destination. If the frame is not dropped, then the TxQ manager links the frame’s FCB to the correct per-port-
per-class TxQ. Unicast TxQ’s are linked lists of transmission jobs, represented by their associated frames’ FCB’s.
There is one linked list for each transmission class for each port. There are 4 transmission classes for each of the
24 10/100 ports and 8 classes for each of the two Gigabit ports – a total of 112 unicast queues.
The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a
port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for
another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among
the head-of-line (HOL) frames from the per-class queues for that port using a Zarlink Semiconductor scheduling
algorithm.
MVTX2600
MVTX2600
MVTX2600
. . .
MVTX2600
MVTX2600
MVTX2600
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