參數(shù)資料
型號: MT9196AE1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Integrated Digital Phone Circuit (IDPC)
中文描述: SPECIALTY TELECOM CIRCUIT, PDIP28
封裝: 0.600 INCH, LEAD FREE, PLASTIC, MS-011AB, DIP-28
文件頁數(shù): 40/46頁
文件大?。?/td> 631K
代理商: MT9196AE1
MT9196
Data Sheet
40
Zarlink Semiconductor Inc.
Timing is over recommended temperature range & recommended power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
Figure 14 - SSI Asynchronous Timing Diagram
AC Electrical Characteristics
- SSI BUS Asynchronous Timing (note 1) (see Figure 14)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
Bit Cell Period
T
DATA
7812
3906
ns
ns
ns
ns
BCL=128 kHz
BCL=256 kHz
2
3
Frame Jitter
Bit 1 Dout Delay from STB
going high
Bit 2 Dout Delay from STB
going high
Bit n Dout Delay from STB
going high
T
j
600
T
j
+600
t
dda1
C
L
=150 pF, R
L
=1K
4
t
dda2
600+
T
DATA
-T
j
600 +
(n-1) x
T
DATA
-T
j
600+
T
DATA
600 +
(n-1) x
T
DATA
600 +
T
DATA
+T
j
600 +
(n-1) x
T
DATA
+T
j
ns
C
L
=150 pF, R
L
=1K
5
t
ddan
ns
C
L
=150 pF, R
L
=1K
n=3 to 8
6
7
Bit 1 Data Boundary
Din Bit n Data Setup time from
STB rising
T
DATA1
t
SU
T
DATA
-T
j
T
DATA
\2
+500ns-T
j
+(n-1) x
T
DATA
T
DATA
\2
+500ns+T
j
+(n-1) x
T
DATA
T
DATA
+T
j
ns
ns
n=1-8
8
Din Data Hold time from STB
rising
t
ho
ns
Din
Dout
STB
70%
30%
70%
30%
70%
30%
T
j
t
dda1
NOTE:
Levels refer to% V
DD
(CMOS I/O)
t
dha1
T
DATA1
t
dda2
T
DATA
Bit 1
Bit 2
Bit 3
D1
D2
D3
t
ho
t
su
T
DATA
/2
T
DATA
T
DATA
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