參數(shù)資料
型號(hào)： MT9196AE1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Integrated Digital Phone Circuit (IDPC)
中文描述： SPECIALTY TELECOM CIRCUIT, PDIP28
封裝： 0.600 INCH, LEAD FREE, PLASTIC, MS-011AB, DIP-28
文件頁(yè)數(shù)： 12/46頁(yè)
文件大?。?/td> 631K
代理商： MT9196AE1
MT9196
Data Sheet
12
Zarlink Semiconductor Inc.
Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
Figure 7 - ST-BUS Channel Assignment
Flexible Digital Interface
A serial link is required to transport data between the IDPC and an external digital transmission device. IDPC
utilizes the ST-BUS architecture defined by Zarlink Semiconductor but also supports a strobed data interface found
on many standard CODEC devices. This interface is commonly referred to as Synchronous Serial Interface (SSI).
The combination of ST-BUS and SSI provides a Flexible Digital Interface (FDI) capable of supporting all Zarlink
basic rate transmission devices as well as many other 2B + D transceivers.
The required mode of operation is selected via the ST-BUS/SSI control bit (FDI Control Register, address 10h). Pin
definitions alter dependent upon the operational mode selected, as described in the following subsections as well
as in the Pin Description tables.
Quiet Code
The FDI can be made to send quiet code to the decoder and receive filter path by setting the RxMUTE bit high.
Likewise, the FDI will send quiet code in the transmit (DSTo) path when the TxMUTE bit is high. Both of these
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
y
COMMAND/ADDRESS
DATA INPUT/OUTPUT
COMMAND/ADDRESS:
DATA 2
RECEIVE
DATA 1
TRANSMIT
SCLK
CS
R/W
X
A
4
A
3
A
2
A
1
A
0
X
D
7
D
0
Delays due to internal processor timing which are transparent to IDPC.
The IDPC:- latches received data on the rising edge of SCLK.
- outputs transmit data on the falling edge of SCLK.
y
The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
The COMMAND/ADDRESS byte contains:
1 bit - Read/Write
5 bits - Addressing Data
2 bits - Unused
F0i
DSTi,
DSTo
LSB first
for D-
Channel
MSB first for C, B1- & B2-
Channels
CHANNEL 0
D-channel
CHANNEL 1
C-channel
CHANNEL 2
B1-channel
CHANNEL 3
B2-channel
CHANNELS 4-31
Not Used
125
μ
s
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