參數(shù)資料
型號(hào)： MT9196AE1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Integrated Digital Phone Circuit (IDPC)
中文描述： SPECIALTY TELECOM CIRCUIT, PDIP28
封裝： 0.600 INCH, LEAD FREE, PLASTIC, MS-011AB, DIP-28
文件頁數(shù)： 4/46頁
文件大?。?/td> 631K
代理商： MT9196AE1
MT9196
Data Sheet
4
Zarlink Semiconductor Inc.
The IDPC features complete Analog/Digital and Digital/Analog conversion of audio signals (Filter/CODEC) and an
analog interface to electro-acoustic devices (Transducer Interface). Full programmability of the receive path and
side-tone gains is available to set comfortable listening levels for the user. Transmit path gain control is available for
setting nominal transmit levels into the network. A digital, anti-feedback circuit permits both the handset microphone
and the speaker-phone speaker to be enabled at the same time for group listening applications. This anti-feedback
circuit limits the total loop gain there by preventing a singing condition from developing.
Signalling in digital telephone systems, behind the PBX or standard ISDN applications, is handled on the D-channel
and generally does not require DTMF tones. Locally generated tones, in the set, however, can be used to provided
“comfort tones” or “key confirmation” to the user, similar to the familiar DTMF tones generated by conventional
phones during initial call set-up. Also, as the network slowly evolves from the dial pulse/DTMF methods to the D-
Channel protocols it is essential that the older methods be available for backward compatibility. As an example,
once a call has been established (i.e., from your office to your home) using the D-Channel signalling protocol it may
be necessary to use in-band DTMF signalling to manipulate your personal answering machine in order to retrieve
messages. Thus the locally generated tones must be of network quality. The IDPC can generate the required tone
pairs as well as single tones to accommodate any in-band signalling requirement.
Each of the programmable parameters within the functional blocks is accessed through a serial microcontroller
port compatible with Intel MCS-51
, Motorola SPI
and National Semiconductor Microwire
specifications.
Functional Description
In this section each of the functional blocks within IDPC is described along with all of the associated control/status
bits. Each time a control/status bit(s) is described it is followed by the address register where it will be found. The
reader is referred to the section titled 'Register Summary' for a complete listing of all address registers, the
control/status bits associated with each register and a definition of the function of each control/status bit. The
Register Summary is useful for future reference of control/status bits without the need to locate them in the text of
the functional descriptions.
Filter/CODEC
The Filter/CODEC block implements conversion of the analog 3.3 kHz speech signals to/from the digital domain
compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are
register programmable. These are CCITT G.711 A-law or
μ
-Law, with true-sign/ Alternate Digit Inversion or true-
sign/Inverted Magnitude coding, respectively. Optionally, sign- magnitude coding may also be selected for
proprietary applications.
The Filter/CODEC block also implements transmit and receive audio path gains in the analog domain. These gains
are in addition to the digital gain pad section and provide an overall path gain resolution of 1.0 dB. A programmable
gain, voice side-tone path is also included to provide proportional transmit speech feedback to the handset receiver.
Figure 3 depicts the nominal half-channel and side-tone gains for the IDPC.
On PWRST (pin 5) the Filter/CODEC defaults such that the side-tone path, dial tone filter and 400 Hz transmit filter
are off, all programmable gains are set to 0 dB and CCITT
μ
-Law is selected. Further, the Filter/CODEC is powered
down due to the control bits of the Path Control Registers (addresses 12h and 13h) being reset.
The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide
dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the Transducer
Interface section to provide full chip realization of these capabilities for the handset and loudspeaker functions.
A reference voltage (V
Ref
), for the conversion requirements of the CODEC section, and a bias voltage (V
Bias
), for
biasing the internal analog sections, are both generated on-chip. V
Bias
is also brought to an external pin so that it
may be used for biasing external gain plan setting amplifiers. A 0.1
μ
F capacitor must be connected from V
Bias
to
analog ground at all times. Likewise, although V
Ref
may only be used internally, a 0.1
μ
F capacitor from the V
Ref
pin
to ground is required at all times. The analog ground reference point for these two capacitors must be physically the
same point. To facilitate this the V
Ref
and V
Bias
pins are situated on adjacent pins.
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