參數(shù)資料
型號： MT9196AE1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 通信及網(wǎng)絡
英文描述： Integrated Digital Phone Circuit (IDPC)
中文描述： SPECIALTY TELECOM CIRCUIT, PDIP28
封裝： 0.600 INCH, LEAD FREE, PLASTIC, MS-011AB, DIP-28
文件頁數(shù)： 35/46頁
文件大?。?/td> 631K
代理商： MT9196AE1
MT9196
Data Sheet
35
Zarlink Semiconductor Inc.
AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Note: RxINC, refer to Control Register 2, address 0Fh.
AC Characteristics
for D/A (Receive) Path
- 0dBm0 = 1.421V
rms
for
μ
-Law and 1.477V
rms
for A-Law, at the CODEC. (V
Ref
=1.0
volts and V
Bias
=2.5 volts.)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
Analog output at the CODEC full
scale
Absolute half-channel gain
A
Lo3.17
A
Lo3.14
5.704
5.906
Vp-p
Vp-p
μ
-Law
A-Law
Receive filter gain = 0dB
setting. Digital gain = 0dB
setting.
RxINC = 0*
RxINC = 1*
2
PCM to HSPKR
±
PCM to SPKR
±
PCM to AUXout
G
AR1
G
AR2
G
AR3
G
AR4
-13.1
-10.6
-1.0
-14
-12.1
-9.6
0
-12
-11.1
-8.6
1.0
-10
dB
dB
dB
dB
@1020 Hz
Tolerance at all other receive
filter settings (-1 to -7dB)
Gain tracking vs. input level
CCITT G.714 Method 2
-0.2
+0.2
dB
3
G
TR
-0.3
-0.6
-1.6
35
29
24
0.3
0.6
1.6
dB
dB
dB
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
0 to -30 dBm0
-40 dBm0
-45 dBm0
μ
-Law
A-Law
4
Signal to total distortion vs. input
level
CCITT G.714 Method 2
Receive Idle Channel Noise
G
QR
5
N
CR
N
PR
G
RR
13
-78.5
15.5
-77
dBrnC0
dBm0p
6
Gain relative to gain at 1020Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz
Absolute Delay
Group Delay relative to D
AR
-0.25
-0.90
0.25
0.25
0.25
-12.5
-25
dB
dB
dB
dB
dB
μ
s
μ
s
μ
s
μ
s
μ
s
dB
dB
7
8
D
AR
D
DR
240
750
380
130
750
at frequency of min. delay
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
G.714.16
9
Crosstalk
D/A to A/D
A/D to D/A
CT
RT
CT
TR
-74
-80
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相關代理商/技術參數(shù)
參數(shù)描述
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