參數(shù)資料
型號: MT9196AE1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Integrated Digital Phone Circuit (IDPC)
中文描述: SPECIALTY TELECOM CIRCUIT, PDIP28
封裝: 0.600 INCH, LEAD FREE, PLASTIC, MS-011AB, DIP-28
文件頁數(shù): 39/46頁
文件大?。?/td> 631K
代理商: MT9196AE1
MT9196
Data Sheet
39
Zarlink Semiconductor Inc.
Timing is over recommended temperature range & recommended power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
Figure 13 - SSI Synchronous Timing Diagram
AC Electrical Characteristics
- SSI BUS Synchronous Timing (see Figure 13)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
2
3
4
5
6
7
8
BCL Clock Period
BCL Pulse Width High
BCL Pulse Width Low
BCL Rise/Fall Time
Strobe Pulse Width
Strobe setup time before BCL falling
Strobe hold time after BCL falling
Dout High Impedance to Active Low
from Strobe rising
Dout High Impedance to Active High
from Strobe rising
10 Dout Active Low to High Impedance
from Strobe falling
11 Dout Active High to High Impedance
from Strobe falling
12 Dout Delay (high and low) from BCL
rising
13 Din Setup time before BCL falling
14 Din Hold Time from BCL falling
t
BCL
t
BCLH
t
BCLL
t
R
/t
F
t
ENW
t
SSS
t
SSH
t
DOZL
244
1953
ns
ns
ns
ns
ns
ns
ns
ns
BCL=4096 kHz to 512 kHz
BCL=4096 kHz
BCL=4096 kHz
Note 1
Note 1
122
122
20
8 x t
BCL
80
80
t
BCL
-80
t
BCL
-80
90
C
L
=150 pF, R
L
=1K
9
t
DOZH
90
ns
C
L
=150 pF, R
L
=1K
t
DOLZ
90
ns
C
L
=150 pF, R
L
=1K
t
DOHZ
90
ns
C
L
=150 pF, R
L
=1K
t
DD
90
ns
C
L
=150 pF
t
DIS
t
DIH
50
50
ns
ns
(BCL)
Din
Dout
STB
70%
30%
70%
30%
70%
30%
70%
30%
t
BCLH
t
R
t
F
t
BCLL
t
DIS
t
DIH
t
DOZL
t
DD
t
BCL
t
DOZH
t
SSS
t
ENW
t
SSH
t
DOLZ
t
DOHZ
NOTE:
Levels refer to% V
DD
(CMOS I/O)
CLOCKin
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