參數(shù)資料
型號： MT48V4M32LFFC
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁數(shù)： 40/61頁
文件大?。?/td> 1400K
代理商： MT48V4M32LFFC
40
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x16, x32
MOBILE SDRAM
ADVANCE
INITIALIZE AND LOAD MODE REGISTER
1,2
*CAS latency indicated in parentheses.
-8
-10
SYMBOL*
t
CKH
t
CKS
t
CMH
t
CMS
t
MRD
3
t
RFC
t
RP
MIN
1
2.5
1
2.5
2
80
20
MAX
MIN
1
2.5
1
2.5
2
100
20
MAX
UNITS
ns
ns
ns
ns
t
CK
ns
ns
TIMING PARAMETERS
-8
-10
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CK (1)
MIN
1
2.5
3
3
8
10
20
MAX
MIN
1
2.5
3
3
10
12
25
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
CKE
BA0, BA1
Load Extended
Mode Register
Load Mode
Register
t
CKS
Power-up:
V
DD
and
CLK stable
T = 100μs
t
CKH
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DQML, DQMU
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DQ
High-Z
A0-A9, A11
RA
A10
RA
ALL BANKS
CLK
t
CK
COMMAND
5
LMR
4
NOP
PRE
3
LMR
4
AR
4
AR
4
ACT
4
t
CMS
t
CMH
BA1 = H
tAS
tAH
t
AS
t
AH
BA1 = L
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CODE
CODE
tAS tAH
CODE
CODE
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PRE
ALL BANKS
t
AS
tAH
NOTE:
1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD MODE REGISTER (LMR) command.
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address,
BA = Bank Address
3. Optional refresh command.
4. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur prior to an Active command.
5. Device timing is -10 with 100 MHz clock.
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T0
T1
T3
T5
T7
T9
T19
T29
DON’T CARE
BA
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()()
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()()
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t
RP
t
MRD
t
MRD
t
RP
t
RFC
t
RFC
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