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| 型號： | MT48V4M32LFFC |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 10/61頁 |
| 文件大?。?/td> | 1400K |
| 代理商： | MT48V4M32LFFC |
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10
128Mb: x16, x32 Mobile SDRAM
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x16, x32
MOBILE SDRAM
ADVANCE
NOTE:
1. For full-page accesses: y = 512 (x16), y = 256
(x32).
2. For a burst length of two, A1-A8 (x16) or A1-A7
(x32) select the block-of-two burst; A0 selects
the starting column within the block.
3. For a burst length of four, A2-A8 (x16) or A2-A7
(x32) select the block-of-four burst; A0-A1 select
the starting column within the block.
4. For a burst length of eight, A3-A8 (x16) or A3-
A7 (x32) select the block-of-eight burst; A0-A2
select the starting column within the block.
5. For a full-page burst, the full row is selected
and A0-A8 (x16) or A0-A7 (x32) select the
starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A8 (x16) or A0-A7
(x32) select the unique column to be accessed,
and mode register bit M3 is ignored.
Table 1
Burst Definition
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
A0
0
1
2
0-1
1-0
0-1
1-0
A1 A0
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
A2 A1 A0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
Full
Page
(y)
n = A0-A11
Not Supported
(location 0-y)
Figure 1
Mode Register Definition
Burst Type
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting col-
umn address, as shown in Table 1.
10
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Op Mode
A10
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M10 = “0, 0”
to ensure compatibility
with future devices.
BA0
BA1
M9
M7 M6
M5
M4
M3
M8
M2
M1
M0
M10
11
A11
M11
M12
M13
Reserved**
13
12
** BA1, BA0 = “0, 0”
to prevent Extended
Mode Register.
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