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| 型號： | MT48LC4M16A2F4-6IT:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54 |
| 封裝： | 8 X 8 MM, VFBGA-54 |
| 文件頁數(shù)： | 4/72頁 |
| 文件大?。?/td> | 3455K |
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PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
12
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Functional Description
In general, the 64Mb SDRAM (4 Meg x 4 x 4 banks, 2 Meg x 8 x 4 banks, and 1 Meg x 16 x 4
banks) is a quad-bank DRAM that operates at 3.3V and includes a synchronous interface
(all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s
16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. Each of the
x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. Each of the
x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address bits (x4: A0–A9; x8: A0–A8; x16:
A0–A7) registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. After power is
applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100s delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100s period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands must be
applied.
Once the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
After the idle state, at least two AUTO REFRESH cycles must be performed. After the
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an unknown state, it must be loaded
prior to applying any operational command. If desired, the two AUTO REFRESH
commands can be issued after the LOAD MODE REGISTER command.
36
G1
NC
–
No connect: May be used as address inputs (A12) on the 256Mb and
512Mb devices.
3, 9, 43, 49
A7, B3, C7,
D3
VDDQ
Supply
DQ power: Isolated DQ power on the die for improved noise
immunity.
6, 12, 46,
52
A3, B7, C3,
D7
VSSQ
Supply
DQ ground: Isolated DQ ground on the die for improved noise
immunity.
1, 14, 27
A9, E7, J9
VDD
Supply
Power supply: +3.3V ±0.3V.
28, 41, 54
A1, E3, J1
VSS
Supply
Ground.
Table 4:
Pin/Ball Descriptions
TSOP Pin
Numbers
VFBGA
Ball
Numbers
Symbol
Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC4M16A2F4-75 | 制造商:Micron Technology Inc 功能描述: |
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