參數(shù)資料
型號： MT48LC4M16A2F4-6IT:G
元件分類： DRAM
英文描述： 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54
封裝： 8 X 8 MM, VFBGA-54
文件頁數(shù)： 38/72頁
文件大小： 3455K
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
43
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Concurrent Auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 12 on
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the READ on bank n when registered
(Figures 14 and 15 on page 27). DQM should be used one clock prior to the WRITE com-
mand to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 22
on page 32), with the data-out appearing CL later. The last valid WRITE to bank n will be
data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
charge), the WRITE to bank m will interrupt the WRITE on bank n when registered
(Figure 20 on page 31). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later. The precharge to bank n
will begin when the READ to bank m is registered (Figure 29 on page 37).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The precharge to
bank n will begin when the WRITE to bank m is registered (Figure 30 on page 38).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins
when the READ to bank m is registered. The last valid WRITE to bank n will be data-in regis-
tered one clock prior to the READ to bank m (Figure 31 on page 38).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to
bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is regis-
tered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48LC4M16A2F4-75 制造商:Micron Technology Inc 功能描述:
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