- 您現(xiàn)在的位置：買賣IC網 > PDF目錄229297 > MT48LC4M16A2F4-6IT:G 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54 PDF資料下載
參數(shù)資料
| 型號： | MT48LC4M16A2F4-6IT:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54 |
| 封裝： | 8 X 8 MM, VFBGA-54 |
| 文件頁數(shù)： | 19/72頁 |
| 文件大?。?/td> | 3455K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
26
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
Figure 13:
Random READ Accesses
Note:
Each READ command may be to any bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figures 14 and 15 on
page 27. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQs will go High-Z (or remain
High-Z), regardless of the state of the DQM signal, provided the DQM was active on the
clock just prior to the WRITE command that truncated the READ command. If not, the
second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in,
then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
DON’T CARE
DOUT
n
DOUT
a
DOUT
x
DOUT
m
READ
NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CLK
DQ
DOUT
n
T2
T1
T4
T3
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
DOUT
a
DOUT
x
DOUT
m
READ
NOP
BANK,
COL a
BANK,
COL x
BANK,
COL m
CAS Latency = 2
CAS Latency = 3
TRANSITIONING DATA
相關PDF資料 |
PDF描述 |
|---|---|
| MT46V32M8FG-6TIT:G | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| MT46V32M8BG-6AT:G | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| M29F800FB55N3E2 | 512K X 16 FLASH 5V PROM, 55 ns, PDSO48 |
| MC12L1NZGF | ROTARY SWITCH-12POSITIONS, SP12T, LATCHED, 0.25A, 28VDC, PANEL MOUNT-THREADED |
| MD00S1NCQF | ROTARY SWITCH-6POSITIONS, DP6T, LATCHED, 0.25A, 28VDC, THROUGH HOLE-STRAIGHT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC4M16A2F4-75 | 制造商:Micron Technology Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。