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參數(shù)資料
| 型號： | MT48LC4M16A2F4-6IT:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54 |
| 封裝： | 8 X 8 MM, VFBGA-54 |
| 文件頁數(shù)： | 16/72頁 |
| 文件大小： | 3455K |
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PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
23
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst which is being truncated.
The new READ command should be issued x cycles before the clock edge at which the
last desired data element is valid, where x = CL -1. This is shown in Figure 12 on page 25
for CL = 2 and CL = 3; data element n + 3 is either the last of a burst of four or the last
desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch architecture. A READ command
can be initiated on any clock cycle following a previous READ command. Full-speed
random read accesses can be performed to the same bank, as shown in Figure 13 on
page 26, or each subsequent READ may be performed to a different bank.
Figure 10:
READ Command
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A0–A9: x4
A0–A8: x8
A0–A7: x16
A10
BA0, BA1
DON’T CARE
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A11: x4
A9, A11: x8
A8, A9, A11: x16
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC4M16A2F4-75 | 制造商:Micron Technology Inc 功能描述: |
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