參數(shù)資料
型號： MT48LC4M16A2F4-6IT:G
元件分類： DRAM
英文描述： 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54
封裝： 8 X 8 MM, VFBGA-54
文件頁數(shù)： 20/72頁
文件大?。?/td> 3455K
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
27
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 14
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 15 shows the case where the additional NOP is
needed.
Figure 14:
READ-to-WRITE
Note:
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank. If a burst of one is used, then DQM is not required.
Figure 15:
READ-to-WRITE With Extra Clock Cycle
Note:
CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE
command may be to any bank.
DON’T CARE
READ
NOP
WRITE
NOP
CLK
T2
T1
T4
T3
T0
DQM
DQ
DOUT n
COMMAND
DIN b
ADDRESS
BANK,
COL n
BANK,
COL b
DS
tHZ
t
tCK
TRANSITIONING DATA
DON’T CARE
READ
NOP
DQM
CLK
DQ
DOUT n
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BANK,
COL n
WRITE
DIN b
BANK,
COL b
T5
DS
tHZ
t
TRANSITIONING DATA
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參數(shù)描述
MT48LC4M16A2F4-75 制造商:Micron Technology Inc 功能描述:
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