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| 型號(hào)： | MT47H128M8HQ-3AT |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60 |
| 文件頁(yè)數(shù)： | 94/129頁(yè) |
| 文件大?。?/td> | 9252K |
| 代理商： | MT47H128M8HQ-3AT |
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Precharge:
Starts with registration of a PRECHARGE command and ends when tRP
is met. After tRP is met, the bank will be in the idle state.
Read with au-
to precharge
enabled:
Starts with registration of a READ command with auto precharge ena-
bled and ends when tRP has been met. After tRP is met, the bank will
be in the idle state.
Row activate: Starts with registration of an ACTIVATE command and ends when
tRCD is met. After tRCD is met, the bank will be in the row active state.
Write with au-
to precharge
enabled:
Starts with registration of a WRITE command with auto precharge ena-
bled and ends when tRP has been met. After tRP is met, the bank will
be in the idle state.
5. The following states must not be interrupted by any executable command (DESELECT or
NOP commands must be applied on each positive clock edge during these states):
Refresh:
Starts with registration of a REFRESH command and ends when tRFC is
met. After tRFC is met, the DDR2 SDRAM will be in the all banks idle state.
Accessing
mode
register:
Starts with registration of the LOAD MODE command and ends when
tMRD has been met. After tMRD is met, the DDR2 SDRAM will be in the
all banks idle state.
Precharge
all:
Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. After tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and bursts are not in progress.
8. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
9. May or may not be bank-specific; if multiple banks are to be precharged, each must be
in a valid state for precharging.
10. A WRITE command may be applied after the completion of the READ burst.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Commands
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
67
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT47H64M16HR-3IT | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| MT48LC4M32TG-10 | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| MT48V8M16LFB4-8XT | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC4M32LFB5-10ES:G | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H128M8HQ-3EAT | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-3EIT | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-3EL | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-3IT | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DDR2 SDRAM |
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