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| 型號(hào)： | MT47H128M8HQ-3AT |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.4 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60 |
| 文件頁(yè)數(shù)： | 25/129頁(yè) |
| 文件大?。?/td> | 9252K |
| 代理商： | MT47H128M8HQ-3AT |
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Precharge Power-Down Clock Frequency Change
When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off
and CKE must be at a logic LOW level. A minimum of two differential clock cycles must
pass after CKE goes LOW before clock frequency may change. The device input clock
frequency is allowed to change only within minimum and maximum operating frequen-
cies specified for the particular speed grade. During input clock frequency change, ODT
and CKE must be held at stable LOW levels. When the input clock frequency is changed,
new stable clocks must be provided to the device before precharge power-down may be
exited, and DLL must be reset via MR after precharge power-down exit. Depending on
the new clock frequency, additional LM commands might be required to adjust the CL,
WR, AL, and so forth. Depending on the new clock frequency, an additional LM com-
mand might be required to appropriately set the WR MR9, MR10, MR11. During the
DLL relock period of 200 cycles, ODT must remain off. After the DLL lock time, the
DRAM is ready to operate with a new clock frequency.
Figure 78: Input Clock Frequency Change During Precharge Power-Down Mode
CK
CK#
Command
Valid4
NOP
Address
CKE
DQ
DM
DQS, DQS#
NOP
tCK
Enter precharge
power-down mode
Exit precharge
power-down mode
T0
T1
T3
Ta0
T2
Don’t Care
Valid
tCKE (MIN)3
tXP
LM
DLL RESET
Valid
NOP
tCH
tCL
Ta1
Ta2
Tb0
Ta3
2 x tCK (MIN)1
1 x tCK (MIN)2
tCH
tCL
tCK
ODT
200 x tCK
NOP
Ta4
Previous clock frequency
New clock frequency
Frequency
change
Indicates a break in
time scale
High-Z
tCKE (MIN)3
Notes: 1. A minimum of 2 × tCK is required after entering precharge power-down prior to chang-
ing clock frequencies.
2. When the new clock frequency has changed and is stable, a minimum of 1 × tCK is re-
quired prior to exiting precharge power-down.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Precharge Power-Down Clock Frequency Change
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
120
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H128M8HQ-3EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-3EIT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-3EL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-3IT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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