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| 型號： | MT46V32M8BG-6AT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封裝： | (8 X 14) MM, LEAD FREE,PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 76/93頁 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
76
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 40:
Nonconsecutive WRITE-to-WRITE
Notes:
1. DI b (or n) = data-in from column b (or column n).
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
Figure 41:
Random WRITE Cycles
Notes:
1. DI b (or x or n or a or g) = data-in from column b (or column x, or column n, or column a, or
column g).
2. b', x', n', a' or g' indicate the next data-in following DO b, DO x, DO n, DO a, or DO g,
respectively.
3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown.
4. Each WRITE command may be to any bank.
CK
Command
WRITE
NOP
Address
Bank,
Col b
WRITE
Bank,
Col n
T0
T1
T2
T3
T2n
T4
T5
T4n
T1n
T5n
DQ
DQS
DM
DI
n
DI
b
tDQSS (NOM)
tDQSS
Don’t Care
Transitioning Data
CK#
tDQSS (NOM)
CK
CK#
Command
WRITE
NOP
Address
Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col g
WRITE
Bank,
Col a
T0
T1
T2
T3
T2n
T4
T5
T4n
T1n
T3n
T5n
DQ
DQS
DM
DI
b
DI
b'
DI
x
DI
x'
DI
n
DI
n'
DI
a
DI
a'
DI
g
DI
g'
Don’t Care
Transitioning Data
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