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| 型號： | MT46V32M8BG-6AT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封裝： | (8 X 14) MM, LEAD FREE,PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 36/93頁 |
| 文件大?。?/td> | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
39
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
39d. The driver pull-up current variation, within nominal voltage and temperature
limits, is expected, but not guaranteed, to lie within the inner bounding lines of
the V-I curve of Figure 16 on page 39.
39e. The full ratio variation of the MAX-to-MIN pull-up and pull-down current should
be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V at
the same voltage and temperature.
39f. The full ratio variation of the nominal pull-up to pull-down current should be
unity ±10%, for device drain-to-source voltages from 0.1V to 1.0V.
Figure 15:
Reduced Drive Pull-Down Characteristics
Figure 16:
Reduced Drive Pull-Up Characteristics
40. The voltage levels used are derived from a minimum VDD level and the referenced test
load. In practice, the voltage levels obtained from a properly terminated bus will pro-
vide significantly different voltage values.
41.
VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width ≤ 3ns, and the pulse
width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = –1.5V
for a pulse width ≤ 3ns, and the pulse width can not be greater than 1/3 of the cycle
rate.
42. VDD and VDDQ must track each other.
43. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
0
10
20
30
40
50
60
70
80
0.00.5
1.01.5
2.0
2.5
IOUT
(mA)
VOUT (V)
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0
0.5
1.0
1.5
2.0
2.5
IOUT
(mA)
VDDQ - VOUT (V)
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