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| 型號(hào)： | MT46V32M8BG-6AT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封裝： | (8 X 14) MM, LEAD FREE,PLASTIC, FBGA-60 |
| 文件頁(yè)數(shù)： | 64/93頁(yè) |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
65
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 30:
Random READ Accesses
Notes:
1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).
2. BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL = 8, the following burst interrupts the previous).
3. n', x', b', or g' indicate the next data-out following DO n, DO x, DO b, or DO g, respectively.
4. READs are to an active row in any bank.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
READ
NOP
READ
CL = 2
CL = 2.5
DO
n
DO
x'
DO
g
DO
n'
DO
b
DO
x
DO
b'
DO
n
DO
x'
DO
n'
DO
b
DO
x
DO
b'
T0
T1
T2
T3
T2n
T3n
T4
T5
T4n
T5n
READ
NOP
READ
T0
T1
T2
T3
T2n
T3n
T4
T5
T4n
T5n
CL = 3
DO
n
DO
x'
DO
n'
DO
b
DO
x
DO
b'
READ
NOP
READ
T0
T1
T2
T3
T3n
T4
T5
T4n
T5n
Bank,
Col n
Bank,
Col b
Bank,
Col x
Bank,
Col g
Bank,
Col n
Bank,
Col b
Bank,
Col x
Bank,
Col g
Bank,
Col n
Bank,
Col b
Bank,
Col x
Bank,
Col g
Command
Address
DQS
DQ
CK#
CK
Command
Address
DQS
DQ
CK#
CK
Command
Address
DQS
DQ
CK#
CK
Transitioning Data
Don’t Care
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