參數(shù)資料
型號(hào)： MT46V32M8BG-6AT:G
元件分類： DRAM
英文描述： 32M X 8 DDR DRAM, 0.7 ns, PBGA60
封裝： (8 X 14) MM, LEAD FREE,PLASTIC, FBGA-60
文件頁(yè)數(shù)： 16/93頁(yè)
文件大?。?/td> 3632K
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
21
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Figure 11:
SSTL_2 Clock Input
Notes:
1. CK or CK# may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
2. This provides a minimum of 1.15V to a maximum of 1.35V and is always half of VDDQ.
3. CK and CK# must cross in this region.
4. CK and CK# must meet at least VID(DC) MIN when static and is centered around VMP(DC).
5. CK and CK# must have a minimum 700mV peak-to-peak swing.
6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values for all devices other than -5B.
Table 13:
Clock Input Operating Conditions
Notes: 1–5, 16, 17, 31 apply to the entire table; Notes appear on page 35;
0°C
≤ T
A ≤ +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V (VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V for -5B)
Parameter/Condition
Symbol
Min
Max
Units
Notes
Clock input mid-point voltage: CK and CK#
VMP(DC)
1.15
1.35
V
Clock input voltage level: CK and CK#
VIN(DC)–0.3
VDDQ + 0.3
V
Clock input differential voltage: CK and CK#
VID(DC)0.36
VDDQ + 0.6
V
Clock input differential voltage: CK and CK#
VID(AC)0.7
VDDQ + 0.6
V
Clock input crossing point voltage: CK and CK#
VIX(AC)
0.5 × VDDQ - 0.2
0.5 × VDDQ + 0.2
V
CK
CK#
2.80V
Maximum clock level
1
Minimum clock level1
–0.30V
1.25V
1.45V
1.05V
VID(AC)
5
VID(DC)
4
X
VMP(DC)
2 VIX(AC)3
X
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