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參數(shù)資料
| 型號(hào)： | MT46V32M8BG-6AT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封裝： | (8 X 14) MM, LEAD FREE,PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 18/93頁 |
| 文件大小： | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
23
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Electrical Specifications – DC and AC
Table 18:
Electrical Characteristics and Recommended AC Operating Conditions (-5B)
0°C
≤ T
A ≤ +70°C; VDDQ = +2.6V ±0.1V, VDD = +2.6V ±0.1V
AC Characteristics
-5B
Units
Notes
Parameter
Symbol
Min
Max
Access window of DQ from CK/CK#
tAC
–0.70
+0.70
ns
CK high-level width
tCH
0.45
0.55
tCK
Clock cycle time
CL = 3
tCK (3)
5
7.5
ns
CL = 2.5
tCK (2.5)
6
13
ns
CL = 2
tCK (2)
7.5
13
ns
CK low-level width
tCL
0.45
0.55
tCK
DQ and DM input hold time relative to DQS
tDH
0.40
–
ns
DQ and DM input pulse width (for each input)
tDIPW
1.75
–
ns
Access window of DQS from CK/CK#
tDQSCK
–0.60
+0.60
ns
DQS input high pulse width
tDQSH
0.35
–
tCK
DQS input low pulse width
tDQSL
0.35
–
tCK
DQS–DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
–
0.40
ns
WRITE command to first DQS latching transition
tDQSS
0.72
1.28
tCK
DQ and DM input setup time relative to DQS
tDS
0.40
–
ns
DQS falling edge from CK rising – hold time
tDSH
0.2
–
tCK
DQS falling edge to CK rising – setup time
tDSS
0.2
–
tCK
Half-clock period
tHP
tCH,tCL
–
ns
Data-out High-Z window from CK/CK#
tHZ
–
+0.70
ns
Address and control input hold time (slew rate
≥0.5 V/ns)
tIH
F
0.60
–
ns
Address and control input pulse width (for each input)
tIPW
2.2
–
ns
Address and control input setup time (slew rate
≥0.5 V/ns)
tIS
F
0.60
–
ns
Data-out Low-Z window from CK/CK#
tLZ
–0.70
–
ns
LOAD MODE REGISTER command cycle time
tMRD
10
–
ns
DQ–DQS hold, DQS to first DQ to go non-valid, per access
tQH
tHP -tQHS
–
ns
Data hold skew factor
tQHS
–
0.50
ns
ACTIVE-to-READ with auto precharge command
tRAP
15
–
ns
ACTIVE-to-PRECHARGE command
tRAS
40
70,000
ns
ACTIVE-to-ACTIVE/AUTO REFRESH command period
tRC
55
–
ns
ACTIVE-to-READ or WRITE delay
tRCD
15
–
ns
REFRESH-to-REFRESH command interval
tREFC
–
70.3
s
REFRESH-to-REFRESH command interval (Automotive)
tREFC
AT
–
17.55
s
Average periodic refresh interval
tREFI
–
7.8
s
Average periodic refresh interval (Automotive)
tREFI
AT
–1.95
s
AUTO REFRESH command period
tRFC
70
–
ns
PRECHARGE command period
tRP
15
–
ns
DQS read preamble
tRPRE
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
10
–
ns
Terminating voltage delay to VDD
tVTD
0
–
ns
DQS write preamble
tWPRE
0.25
–
tCK
DQS write preamble setup time
tWPRES
0
–
ns
DQS write postamble
tWPST
0.4
0.6
tCK
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