
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
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256Mb_DDR_x4x8x16_D1.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
2
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Features
Notes:
1. The -5B device is backward compatible with all slower speed grades. The voltage range of
-5B device operating at slower speed grades is VDD = VDDQ = 2.5V ± 0.2V.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency; MIN clock rate with 50% duty cycle at CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and
CL = 3 (-5B)
Speed Grade
Clock Rate (MHz)
Data-Out Window Access Window DQS–DQ Skew
CL = 2
CL = 2.5
CL = 3
-5B
133
167
200
1.6ns
±0.70ns
+0.40ns
-6
133
167
n/a
2.1ns
±0.70ns
+0.40ns
6T
133
167
n/a
2.0ns
±0.70ns
+0.45ns
-75E/-75Z
133
n/a
2.5ns
±0.75ns
+0.50ns
-75
100
133
n/a
2.5ns
±0.75ns
+0.50ns
Table 2:
Addressing
Parameter
64 Meg x 4
32 Meg x 8
16 Meg x 16
Configuration
16 Meg x 4 x 4 banks
8 Meg x 8 x 4 banks
4 Meg x 16 x 4 banks
Refresh count
8K
Row address
8K (A0–A12)
Bank address
4 (BA0, BA1)
Column address
2K (A0–A9, A11)
1K (A0–A9)
512 (A0–A8)
Table 3:
Speed Grade Compatibility
Marking
PC3200 (3-3-3) PC2700 (2.5-3-3) PC2100 (2-2-2) PC2100 (2-3-3) PC2100 (2.5-3-3) PC1600(2-2-2)
-5B1
Yes
-6
–
Yes
-6T
–
Yes
-75E
–
Yes
-75Z
–
Yes
-75
––
–
Yes
-5B
-6/-6T
-75E
-75Z
-75