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| 型號(hào)： | MT46H32M32LGCM-5IT:A |
| 元件分類： | DRAM |
| 英文描述： | 32M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封裝： | 10 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件頁(yè)數(shù)： | 72/95頁(yè) |
| 文件大?。?/td> | 3231K |
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Figure 38: WRITE-to-READ – Uninterrupting
tDQSSnom
CK
CK#
Command1
WRITE2,3
NOP
READ
NOP
Address
Bank a,
Col b
Bank a,
Col n
NOP
T0
T1
T2
T3
T2n
T4
T5
T1n
T6
T6n
tWTR4
CL = 2
DQ5
DQS
DM
tDQSS
tDQSSmin
CL = 2
DQ5
DQS
DM
tDQSS
tDQSSmax
CL = 2
DQ5
DQS
DM
tDQSS
Don’t Care
Transitioning Data
T5n
DIN
DOUT
DIN
DOUT
DIN
Notes: 1. The READ and WRITE commands are to the same device. However, the READ and WRITE
commands may be to different devices, in which case tWTR is not required and the
READ command could be applied earlier.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. An uninterrupted burst of 4 is shown.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. DINb = data-in for column b; DOUTn = data-out for column n.
1Gb: x16, x32 Mobile LPDDR SDRAM
WRITE Operation
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. K 07/09 EN
74
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2007 Micron Technology, Inc. All rights reserved.
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