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參數資料
| 型號： | MT46H32M32LGCM-5IT:A |
| 元件分類： | DRAM |
| 英文描述： | 32M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封裝： | 10 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件頁數： | 13/95頁 |
| 文件大?。?/td> | 3231K |
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Electrical Specifications – IDD Parameters
Table 7: IDD Specifications and Conditions (x16)
Notes 1–5 apply to all the parameters/conditions in this table; VDD/VDDQ = 1.70–1.95V
Parameter/Condition
Symbol
Max
Unit Notes
-5
-54
-6
-75
Operating 1 bank active precharge current: tRC = tRC (MIN); tCK =
tCK (MIN); CKE is HIGH; CS is HIGH between valid commands; Ad-
dress inputs are switching every 2 clock cycles; Data bus inputs
are stable
IDD0
80
75
70
60
mA
Precharge power-down standby current: All banks idle; CKE is
LOW; CS is HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
IDD2P
600
μA
Precharge power-down standby current: Clock stopped; All banks
idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
IDD2PS
600
μA
Precharge nonpower-down standby current: All banks idle; CKE =
HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs are
switching; Data bus inputs are stable
IDD2N
18
17
15
12
mA
Precharge nonpower-down standby current: Clock stopped; All
banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
IDD2NS
14
13
8
mA
Active power-down standby current: 1 bank active; CKE = LOW;
CS = HIGH; tCK = tCK (MIN); Address and control inputs are switch-
ing; Data bus inputs are stable
IDD3P
3.6
mA
Active power-down standby current: Clock stopped; 1 bank ac-
tive; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
IDD3PS
3.6
mA
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS =
HIGH; tCK = tCK (MIN); Address and control inputs are switching;
Data bus inputs are stable
IDD3N
20
19
18
16
mA
Active nonpower-down standby: Clock stopped; 1 bank active;
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and con-
trol inputs are switching; Data bus inputs are stable
IDD3NS
14
12
mA
Operating burst read: 1 bank active; BL = 4; tCK = tCK (MIN); Con-
tinuous READ bursts; IOUT = 0mA; Address inputs are switching
every 2 clock cycles; 50% data changing each burst
IDD4R
130
125
115
105
mA
Operating burst write: 1 bank active; BL = 4; tCK = tCK (MIN); Con-
tinuous WRITE bursts; Address inputs are switching; 50% data
changing each burst
IDD4W
130
125
115
105
mA
Auto refresh: Burst refresh; CKE = HIGH; Ad-
dress and control inputs are switching; Data bus
inputs are stable
tRFC = 138ns
IDD5
140
mA
tRFC = tREFI
IDD5A
15
14
mA
Typical deep power-down current at 25°C: Address and control
balls are stable; Data bus inputs are stable
IDD8
10
μA
1Gb: x16, x32 Mobile LPDDR SDRAM
Electrical Specifications – IDD Parameters
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. K 07/09 EN
20
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2007 Micron Technology, Inc. All rights reserved.
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