參數(shù)資料
型號(hào)： MT46H32M32LGCM-5IT:A
元件分類(lèi)： DRAM
英文描述： 32M X 32 DDR DRAM, 5 ns, PBGA90
封裝： 10 X 13 MM, GREEN, PLASTIC, VFBGA-90
文件頁(yè)數(shù)： 26/95頁(yè)
文件大?。?/td> 3231K
Commands
A quick reference for available commands is provided in Table 14 and Table 15
(page 33), followed by a written description of each command. Three additional truth
commands and current/next state information.
Table 14: Truth Table – Commands
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN; all states and sequences not shown
are reserved and/or illegal
Name (Function)
CS#
RAS#
CAS#
WE#
Address
Notes
DESELECT (NOP)
H
X
NO OPERATION (NOP)
L
H
X
ACTIVE (select bank and activate row)
L
H
Bank/row
READ (select bank and column, and start READ burst)
L
H
L
H
Bank/column
WRITE (select bank and column, and start WRITE burst)
L
H
L
Bank/column
BURST TERMINATE or DEEP POWER-DOWN (enter deep
power-down mode)
L
H
L
X
PRECHARGE (deactivate row in bank or banks)
L
H
L
Code
AUTO REFRESH (refresh all or single bank) or SELF RE-
FRESH (enter self refresh mode)
L
H
X
LOAD MODE REGISTER
L
Op-code
Notes: 1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A[0:I] provide row address (where I = the most signif-
icant address bit for each configuration).
3. BA0–BA1 provide bank address; A[0:I] provide column address (where I = the most signif-
icant address bit for each configuration); A10 HIGH enables the auto precharge feature
(nonpersistent); A10 LOW disables the auto precharge feature.
4. Applies only to READ bursts with auto precharge disabled; this command is undefined
and should not be used for READ bursts with auto precharge enabled and for WRITE bursts.
5. This command is a BURST TERMINATE if CKE is HIGH and DEEP POWER-DOWN if CKE is
LOW.
6. A10 LOW: BA0–BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8. Internal refresh counter controls row addressing; in self refresh mode all inputs and I/Os
are “Don’t Care” except for CKE.
9. BA0–BA1 select the standard mode register, extended mode register, or status register.
1Gb: x16, x32 Mobile LPDDR SDRAM
Commands
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. K 07/09 EN
32
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2007 Micron Technology, Inc. All rights reserved.
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