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參數(shù)資料
| 型號： | MT29F4G08FABWGXXXXET |
| 元件分類： | PROM |
| 英文描述： | 512M X 8 FLASH 2.7V PROM, PDSO48 |
| 封裝： | TSOP1-48 |
| 文件頁數(shù)： | 24/57頁 |
| 文件大?。?/td> | 730K |
| 代理商： | MT29F4G08FABWGXXXXET |
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09005aef818a56a7 pdf/ 09005aef81590bdd source
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2gb_nand_m29b__2.fm - Rev. C 5/05 EN
30
2004 Micron Technology, Inc. All rights reserved.
2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory
Command Definitions
PROGRAM PAGE CACHE MODE 80h–15h
Cache programming is actually a buffered programming mode of the standard PAGE
PROGRAM command. Programming is started by loading the SERIAL DATA INPUT
(80h) command to the command register, followed by five cycles of address, and a full or
partial page of data. The data is initially copied into the cache register, and the CACHE
WRITE (15h) command is then latched to the command register. Data is transferred
from the cache register to the data register on the rising edge of WE#. R/B# goes LOW
during this transfer time. After the data has been copied into the data register and R/B#
returns to HIGH, memory array programming begins.
When R/B# returns to HIGH, new data can be written to the cache register by issuing
another CACHE PROGRAM command sequence. The time that R/B# stays LOW will be
controlled by the actual programming time. The first time through equals the time it
takes to transfer the cache register contents to the data register. On the second and sub-
sequent programming passes, transfer from the cache register to the data register is held
off until current data register content has been programmed into the array.
Bit 6 (Cache R/B#) of the status register can be read by issuing the READ STATUS (70h)
command to determine when the cache register is ready to accept new data. The R/B#
pin always follows bit 6.
Bit 5 (R/B#) of the status register can be polled to determine when the actual program-
ming of the array is complete for the current programming cycle.
If just the R/B# pin is used to determine programming completion, the last page of the
program sequence must use the PROGRAM PAGE (10h) command instead of the
CACHE PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used
every time, including the last page of the programming sequence, status register bit 5
must be used to determine when programming is complete. (See Figure 24.)
Bit 0 of the status register returns the pass/fail for the previous page when bit 6 of the
status register is a “1” (ready state). The pass/fail status of the current PROGRAM opera-
tion is returned with bit 0 of the status register when bit 5 of the status register is a “1”
(ready state). (See Figure 24.)
Figure 24:
PROGRAM PAGE CACHE MODE Example
Notes: 1. See Note 3, Table 19 on page 42.
2. Check I/O[6:5] for internal Ready/Busy. Check I/O[1:0] for pass fail. RE# can stay LOW or
pulse multiple times after a 70h command.
tCBSY
R/B#
I/Ox
R/B#
I/Ox
Address &
Data Input
80h
15h
Address &
Data Input
80h
15h
Address &
Data Input
80h
15h
Address &
Data Input
80h
10h
tCBSY
tLPROG1
tCBSY
Address &
Data Input
80h
15h
Address &
Data Input
80h
10h
Status2
Output
70h
tPROG
Status2
Output
70h
A: Without status reads.
B: With status reads.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT29F4G16ABADAH4 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory Features |
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