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參數(shù)資料
| 型號(hào)： | MSP34X1G |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Multistandard Sound Processor Family with Virtual Dolby Surround |
| 中文描述： | 多標(biāo)準(zhǔn)聲音處理器系列與虛擬杜比環(huán)繞聲 |
| 文件頁(yè)數(shù)： | 86/104頁(yè) |
| 文件大?。?/td> | 871K |
| 代理商： | MSP34X1G |
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MSP 34x1G
PRELIMINARY DATA SHEET
86
Micronas
6.2. DSP Write and Read Registers for Manual/Compatibility Mode
Table 6
–
2:
Demodulator Read Registers; Subaddress: 11
hex
; these registers are not writable!
Demodulator
Read Registers
Address
(hex)
MSP-
Version
Description
Page
C_AD_BITS
00 23
3411,
3451
NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits
95
ADD_BITS
00 38
NICAM: bit[10:3] of additional data bits
95
CIB_BITS
00 3E
NICAM: CIB1 and CIB2 control bits
95
ERROR_RATE
00 57
NICAM error rate, updated with 182 ms
96
PLL_CAPS
02 1F
Not for customer use
96
AGC_GAIN
02 1E
Not for customer use
96
Table 6
–
3:
DSP-Write Registers; Subaddress: 12
hex
, all registers are readable as well
Write Register
Address
(hex)
Bits
Operational Modes and Adjustable Range
Reset
Mode
Page
Volume SCART1 channel: Ctrl. mode
00 07
[7:0]
[Linear mode / logarithmic mode]
00
hex
97
FM Fixed Deemphasis
00 0F
[15:8]
[50
μ
s, 75
μ
s, J17, OFF]
50
μ
s
97
FM Adaptive Deemphasis
[7:0]
[OFF, WP1]
OFF
97
Identification Mode
00 15
[7:0]
[B/G, M]
B/G
98
FM DC Notch
00 17
[7:0]
[ON, OFF]
ON
98
Volume SCART2 channel: Ctrl. mode
00 40
[7:0]
[Linear mode / logarithmic mode]
00
hex
97
Table 6
–
4:
DSP Read Registers; Subaddress: 13
hex
, all registers are not writable
Additional Read Registers
Address
(hex)
Bits
Output Range
Page
Stereo detection register for
A2 Stereo Systems
00 18
[15:8]
[80
hex
... 7F
hex
]
8 bit two
’
s complement
98
DC level readout FM1/Ch2-L
00 1B
[15:0]
[8000
hex
... 7FFF
hex
]
16 bit two
’
s complement
98
DC level readout FM2/Ch1-R
00 1C
[15:0]
[8000
hex
... 7FFF
hex
]
16 bit two
’
s complement
98
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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