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參數(shù)資料
| 型號： | MSP34X1G |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Multistandard Sound Processor Family with Virtual Dolby Surround |
| 中文描述： | 多標(biāo)準(zhǔn)聲音處理器系列與虛擬杜比環(huán)繞聲 |
| 文件頁數(shù)： | 19/104頁 |
| 文件大?。?/td> | 871K |
| 代理商： | MSP34X1G |
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PRELIMINARY DATA SHEET
MSP 34x1G
Micronas
19
Fig. 3
–
1:
I
2
C bus protocol (MSB first; data must be stable while clock is high)
3.1.4. Proposals for General MSP 34x1G
I
2
C Telegrams
3.1.4.1. Symbols
daw
dar
<
>
aa
dd
write device address (80
hex
, 84
hex
or 88
hex
)
read device address (81
hex
, 85
hex
or 89
hex
)
Start Condition
Stop Condition
Address Byte
Data Byte
3.1.4.2. Write Telegrams
<daw 00 d0 00>
<daw 10 aa aa dd dd>
<daw 12 aa aa dd dd>
write to CONTROL register
write data into demodulator
write data into DSP
3.1.4.3. Read Telegrams
<daw 00 <dar dd dd>
read data from
CONTROL register
<daw 11 aa aa <dar dd dd>
read data from demodulator
<daw 13 aa aa <dar dd dd>
read data from DSP
3.1.4.4. Examples
<80 00 80 00>
<80 00 00 00>
<80 10 00 20 00 03>
<80 11 02 00 <81 dd dd>
Read STATUS
<80 12 00 08 01 20>
RESET MSP statically
Clear RESET
Set demodulator to stand. 03
hex
Set loudspeaker channel
source to NICAM and
Matrix to STEREO
More examples of typical application protocols are
listed in Section 3.4.
“
Programming Tips
”
on page 45.
3.2. Start-Up Sequence:
Power-Up and I
2
C-Controlling
After POWER-ON or RESET (see Fig. 4
–
26), the IC is
in an inactive state. All registers are in the Reset posi-
tion (see Table 3
–
5 and Table 3
–
6), the analog outputs
are muted. The controller has to initialize all registers
for which a non-default setting is necessary.
3.3. MSP 34x1G Programming Interface
3.3.1. User Registers Overview
The MSP 34x1G is controlled by means of user regis-
ters. The complete list of all user registers is given in
Table 3
–
5 and Table 3
–
6. The registers are partitioned
into the Demodulator section (subaddress 10
hex
for
writing, 11
hex
for reading) and the Baseband Process-
ing sections (subaddress 12
hex
for writing, 13
hex
for
reading).
Write and read registers are 16 bit wide, whereby the
MSB is denoted bit[15]. Transmissions via I
2
C bus have
to take place in 16-bit words (two byte transfers, with the
most significant byte transferred first). All write registers,
except the demodulator write registers are readable.
Unused parts of the 16-bit write registers must be zero.
Addresses not given in this table must not be
accessed.
For reasons of software compatibility to the
MSP 34xxD, a Manual/Compatibility Mode is available.
More read and write registers together with a detailed
description can be found in
“
Appendix B: Manual/Com-
patibility Mode
”
on page 85.
1
0
S
P
I2C_DA
I2C_CL
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