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| 型號(hào)： | MSM9225GA-2K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 51/74頁 |
| 文件大?。?/td> | 487K |
| 代理商： | MSM9225GA-2K |
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Semiconductor
MSM9225
55/73
FUNCTIONS
1. Bus priority decisions
(1) When a single node has started transmission
While the bus is idle, the node that outputs data first will transmit.
(2) When multiple nodes have started transmission
Beginning from the 1st bit of the arbitration field, the node that outputs the longest
consecutive string of "dominant" bits will have priority. (Since the bus has a wired-OR
configuration, "dominant" is strong.)
The transmit node compares the arbitration field that it has output with the data levels on the
bus.
Non-matching levels
Matching levels
Data output is terminated from the next bit after non-matching is detedted. The operation
changes to reception.
Transmission continues.
(3) Data frame and remote frame priority
If a data frame and remote frame contend for control of the bus, the data frame whose last bit,
RTR, is "dominant" will be given priority.
2. Bit stuffing
If 5 or more consecutive bits have the same level, bit stuffing prevents a burst error by appending
1 bit of inverted data, and then re-synchronizing.
Reception
Transmission
When receiving a data frame or a remote frame, if there are 5 consecutive bits with the
same level between the start-of-frame and the CRC field, the next bit is deleted and the
data received
When transmitting a data frame or remote frame, if there are 5 consecutive bits with the
same level between the start-of-frame and the CRC field, 1-bit of data at the inverted level
of the previous 5 bits is inserted before the next bit.
3. Multi-master
So that bus priority can be determined by the identifier, any node may become the bus master.
4. Multi-cast
There is one transmit node, however since multiple nodes can be set with the same identifier,
multiple nodes can simultaneously receive the same data.
5. Sleep and stop mode functions
These modes are low-power consuming standby modes.
Setting the SLEEP bit of the STBY register to "1" sets the sleep mode.
(after bus idle)
Setting the STOP bit of the STBY register to "1" sets the stop mode.
(after bus idle)
The sleep mode is released when the Rx0 and Rx1 differential inputs, the RESET pin input, or the
CS pin input is at a "L" level.
The stop mode is released when the RESET pin input or the CS pin input is at a "L" level.
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