參數(shù)資料
型號(hào)： MSM9225GA-2K
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44
封裝： 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
文件頁(yè)數(shù)： 34/74頁(yè)
文件大小： 487K
代理商： MSM9225GA-2K
Semiconductor
MSM9225
4/73
PIN DESCRIPTIONS
Symbol
Type
CS
I
Description
Chip select pin. When "L", PALE, PWR, PRD/SRW, SCLK and SDO pins are valid.
Pin
10
A7-0
I
Address bus pins (when using separate buses). If used with a multiplexed bus or if
used in the serial mode, fix these pins at "H" or "L" levels.
41-44,
1-4
AD7-0
/D7-0
I/O
Multiplexed bus: Address/data pins
Separate buses: Data pins
If used in the serial mode, fix these pins at "H" or "L" levels.
31-38
PWR
I
Write input pin during parallel mode. Data is captured when this pin is at a "L" level.
If used in the serial mode, fix this pin at a "H" or "L" level.
26
RPD/SRW
I
Parallel mode: Read signal pin.
When at a "L" level, data is output from the data pin.
Serial mode: Read/write signal pin.
When at a "H" level, data is output from the SDO pin.
When at a "L" level, the SDO pin is at high impedance, and data is captured beginning
with the second byte of data input from the SDI pin.
9
PALE
I
Address latch signal pin.
When at a "H" level, addresses are captured.
If used in the parallel mode and the address latch signal is unnecessary or in the
serial mode, fix this pin at a "H" or "L" level.
27
SDI
I
Serial data input pin.
Addresses (1st byte) and data (beginning from the 2nd byte) are input to this pin,
LSB first. If used in the parallel mode, fix this pin at a "H" or "L" level.
7
SDO
O
Serial data output pin.
When the CS pin is at a "H" level, this pin is at high impedance. When CS is at a "L"
level, data is output from this pin LSB first.
If used in the parallel mode, fix this pin at a "H" or "L" level.
5
SCLK
I
Shift clock input pin for serial data.
At the rising edge of the shift clock, SDI pin data is captured. At the falling edge, data
is output from the SDO pin.
8
PRDY
/SWAIT
O
Ready output pin.
If the microcontroller's bus cycle is fast, a signal is output to extend the bus cycle
until the internal access is completed.
16
Parallel mode
Serial mode
Internal access in progress
After completion of access
"L" level output
High impedance output
"H" level output
"L" level output
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