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參數(shù)資料
| 型號： | MSM9225GA-2K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 33/74頁 |
| 文件大小： | 487K |
| 代理商： | MSM9225GA-2K |
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Semiconductor
MSM9225
39/73
MICROCONTROLLER INTERFACE
There are basically two methods of interfacing to the microcontroller.
(1) Synchronous serial interface (serial mode)
(2) Parallel bus interface (parallel mode)
Each interface is selected with the Mode0 and Mode1 pins.
Refer to the section, PIN
DESCRIPTIONS, "PIN DESCRIPTIONS" for the relation between pin values and interface
selection.
Serial Interface
The transfer timing is indicated in the figure.
Address/data transfers begin when the CS pin is at a "L" level and end when it changes to a "H"
level. Because the MSM9225 has an address increment function, the basic transfer consists of "1
address + multiple data." Therefore, to access a nonconsecutive address, the CS must be first
pulled to a "H" level, and then the address reset.
Perform address/data transfers LSB first, in 8-byte units. During a transfer, an interval (WAIT)
is necessary between address and data and between consecutive data transfers. (Refer to the
section, ELECTRICAL CHARACTERISTICS, for interval values.) Note that the WAIT signal is
only generated during the interval between address and data transfers.
(1) Data write
Data write operations are performed with the follwing procedure.
After setting the CS pin and PRD/SRW pin to "L" levels, input an address to the SDI pin.
Synchronized to the rising edge of synchronous clock SCLK, the MSM9225 captures the address
in an internal register. When 8 SCLK clocks are received, the MSM9225 loads the address into
the internal address counter and waits for data reception.
Next, input data to the SDI pin. An internal register captures data in a similar manner to the
address capture, at the rising edge of SCLK. When 8 bits of data have been captured, the
MSM9225 writes the data to the internal memory or register specified by the address that was
received previously, and then increments the counter by 1. If data is to be written to consecutive
addresses, continue the data transfer. After all data has been transferred, set the CS pin to a "H"
level.
(2) Data read
Data read operations are performed with the following procedure.
After setting the CS pin to a "L" level and the PRD SRW pin to a "H" level, in the same manner
as for the data write operation, input an address to the SDI pin. When 8 SCLK clocks are received,
the MSM9225 loads the address into the internal address counter, reads data from the internal
memory or register specified by the address, latches data into a shift register for data output and
increments the address counter. Then, when SCLK is input, latched data is output from the SDO
pin synchronized to the falling edge of SCLK. At this time, the contents of the data input from
the SDI pin does not matter. If there exists remaining data to be read, input another 8 SCLK
clocks. After all the data (at consecutive addresses) has been read, set the CS pin to a "H" level.
If the count value overflows (exceeds XFh), without changing the upper 4 bits of the address, the
address increment function will reset the count value of the lower 4 bits to 0, and will continue
counting.
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