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參數(shù)資料
| 型號(hào)： | MSM5416263 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 262,144-Word ×16-Bit Multiport DRAM(256k字×16位多端口動(dòng)態(tài)RAM) |
| 中文描述： | 262,144字× 16位多端口內(nèi)存（256k字× 16位多端口動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 32/40頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MSM5416263 |
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Semiconductor
MSM5416263
32/40
Load/Read Color Register:
RAS
falling edge ---
CAS
=
TRG
=
WEL
=
WEU
= DSF = "H"
CAS
falling edge --- DSF = "H"
The MSM5416263 is provided with an on-chip 16-bit color register for use during the flash write
or block write operation. Each bit of the color register corresponds to one of the DRAM I/O
blocks.
The data presented on the DQi lines is subsequently latched into the color register at the falling
edge of either
CAS
or
WE
whichever occurs later.
The read color register cycle is activated by holding both
WEL
and
WEU
"high" at the falling edge
of
CAS
, and throughout the remainder of the cycle. The data in the color register becomes valid
on the DQi lines after the specified access times from
RAS
and
TRG
are satisfied.
During the load/read color register cycle, the memory cells on the row address latched at the
falling edge of
RAS
are refreshed.
Load/Read Mask Register:
RAS
falling edge ---
CAS
=
TRG
=
WEL
=
WEU
= DSF = "H"
CAS
falling edge --- DSF = "L"
The MSM5416263 is provided with an on-chip 16-bit mask register for use during the mask write
cycle, flash write cycle, block write cycle, masked write transfer, and masked split write transfer.
Each bit of the mask register corresponds to one of the DRAM I/O blocks.
The data presented on the DQi lines is subsequently latched into the mask register at the falling
edge of either
CAS
or
WE
whichever occurs later.
The read mask register cycle is activated by holding both
WEL
and
WEU
"high" at the falling edge
of
CAS
, and throughout the remainder of the cycle. The data in the mask register becomes valid
on the DQi lines after the specified access times from
RAS
and
TRG
are satisfied.
During the load/read mask register cycle, the memory cells on the row address latched at the
falling edge of
RAS
are refreshed.
Flash Write:
RAS
falling edge ---
CAS
=
TRG
= DSF = "H",
WEL
=
WEU
= "L"
Flash write allows for the data in the color register to be written into all the memory locations of
a selected row.
Each bit of the color register corresponds to one of the DRAM I/O blocks. The flash write
operation can be selectively controlled on an I/O basis in the same manner as the write per bit
operation. The mask data is the same as that of a RAM write cycle.
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| MSM54V32126A | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM5416263-60G3-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM5416263-60GS-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM5416273-50G3-K | 制造商:ROHM Semiconductor 功能描述:DUE TO FLOOD DAMAGE TO TESTERS |
| MSM5416273-50GS-K | 制造商:ROHM Semiconductor 功能描述: 制造商:OK International 功能描述:256K X 16 VIDEO DRAM, 50 ns, PDSO64 |
| MSM541627360GSK | 制造商:OK International 功能描述: |
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