參數(shù)資料
型號(hào)： MSM5416263
廠(chǎng)商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 262,144-Word ×16-Bit Multiport DRAM(256k字×16位多端口動(dòng)態(tài)RAM)
中文描述： 262,144字× 16位多端口內(nèi)存（256k字× 16位多端口動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 31/40頁(yè)
文件大小： 389K
代理商： MSM5416263
Semiconductor
MSM5416263
31/40
If the DSF is "high" at the falling edge of
RAS
, special functions such as split transfer, flash write,
load mask register, load color register, CBRS and CBRN can be invoked.
If the DSF is "low" at the falling edge of
RAS
and "high" at the falling edge of
CAS
, the block write
feature can be invoked.
RAM PORT OPERATION
Extended RAM Read Cycle:
RAS
falling edge ---
TRG
=
CAS
= "H", DSF = "L"
CAS
falling edge --- DSF = "L"
The MSM5416263 offers an accelerated page mode cycle (EXTENDED PAGE MODE) by
eliminating output disable from
CAS
"high", and it allows
CAS
precharge time (t
CP
) to occur
without the output data becoming invalid. This new data out operates (Extended data out) as any
RAM read or Page Mode Read, except data will be held valid after
CAS
goes "high", as long as
RAS
is "low".
RAM Write Cycle:
RAS
falling edge ---
TRG
=
CAS
= "H", DSF = "L"
CAS
falling edge --- DSF = "L"
1) Write cycle with no mask:
RAS
falling edge --
WEL
=
WEU
= "H"
If either
WEL
or
WEU
is set "low" at the falling edge of
CAS
after
RAS
goes "low", a write cycle
is excuted. If either
WEL
or
WEU
is set "low" before the
CAS
falling edge, this cycle becomes an
early write cycle, and all DQ pins attain high impedance.
If either
WEL
or
WEU
is "low" when
CAS
goes "low", the write affects only those corresponding
8 bits with the latched data.
If both
WEL
and
WEU
are set "low" after the
CAS
falling edge, this cycle becomes a late write
cycle, and all 16 data are latched on the falling edge of
WEL
or
WEU
.
Byte write occurs if either
WEL
or
WEU
falls during the cycle. DQ pins don't achieve high
impedance in this cycle, so data should be entered with
TRG
in "high".
2) Write cycle with mask:
RAS
falling edge --
WEL
or
WEU
= "L"
If either
WEL
or
WEU
is set "low" at the falling edge of
RAS
, two modes of mask write can be
invoked.
#1 In new mask mode mask data is loaded and used. The mask data on DQ0 - DQ15 is latched
into the write mask register at the falling edge of
RAS
. When the mask data is low, writing is
inhibited into the RAM and the mask data is high, data is written into the RAM. This mask data
is in effect during the
RAS
cycle. In page mode cycle the mask data is retained during page access.
#2 If a load mask register cycle (LMR) has been performed, the mask data is not loaded from DQ
pins, and the mask data stored in the mask register is persistently used.
This operation is known as persistent write mask, set by LMR and reset by CBRR.
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