1422
6437E–ATARM–23-Apr-13
SAM9M11
53.2.2
Reset Controller (RSTC)
53.2.2.1
RSTC: Software reset during DDRAM accesses
When a software reset (CPU and peripherals) occurs during DDRAM read access, the CPU will
stop the DDRAM clock.
The DDRAM maintains the data on the bus until the clock restarts. This will create a bus conflict
if another memory sharing the external bus with the DDRAM is accessed prior to completion of
the read access to the DDRAM. Such a conflict will occur when the device boots out of an exter-
nal NAND or NOR Flash following the software reset.
Problem Fix/Workaround
1.
Boot from Serial Flash
2.
Before generating the software reset, the user must ensure that all the accesses to
DDRAM are completed and then put the DDRAM in self-refresh mode. The routine to
generate the software reset must be located in internal SRAM or in the ARM cache
memory.
53.2.3
Error Corrected Code Controller (ECC)
53.2.3.1
ECC: Computation with a 1 clock cycle long NRD/NWE pulse
If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, ECC cannot com-
pute the parity.
Problem Fix/Workaround
It is recommended to program SMC with a value superior to 1.
53.2.3.2
ECC: Incomplete parity status when error in ECC parity
When a single correctable error is detected in ECC value, the error is located in ECC Parity reg-
ister's field which contains a 1 in the 24 least significant bits except when the error is located in
the 12th or the 24th bit. In this case, these bits are always stuck at 0.
A Single correctable error is detected but it is impossible to correct it.
Problem Fix/Workaround
None.
53.2.3.3
ECC: Unsupported ECC per 512 words
1 bit ECC per 512 words is not functional.
Problem Fix/Workaround
Perform the ECC computation by software.
53.2.3.4
ECC: Unsupported hardware ECC on 16-bit Nand Flash
Hardware ECC on 16-bit Nand Flash is not supported.
Problem Fix/Workaround
Perform the ECC by software.