黄色三级成人毛片,国产精品看高国产精品不卡,99精产国品一二三产区区别

您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25633 > MQ80C52CXXX-36SBR (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 PDF資料下載

型號：	MQ80C52CXXX-36SBR
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
文件頁數(shù)：	1399/1447頁
文件大小：	3788K
代理商：	MQ80C52CXXX-36SBR

6437E–ATARM–23-Apr-13

Functional Description

The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit

mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream

from the image sensor on the 12-bit data bus.

This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the

pixel clock. The reduced pin count alternative for synchronization is supported for sensors that

embed SAV (start of active video) and EAV (end of active video) delimiters in the data stream.

The Image Sensor Interface interrupt line is connected to the Advanced Interrupt Controller and

can trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If

the SAV/EAV synchronization is used, an interrupt can be triggered on each delimiter event.

For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr

4:2:2, RGB 8:8:8, RGB 5:6:5 and may be processed before the storage in memory. The data

stream may be sent on both preview path and codec path if the bit ISI_CDC in the ISI_CTRL is

one. To optimize the bandwidth, the codec path should be enabled only when a capture is

In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit

data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per

word, depending on the GS_MODE bit in the ISI_CFG2 register. The codec datapath is not

available when grayscale image is selected.

A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames.

Data Timing

The two data timings using horizontal and vertical synchronization and EAV/SAV sequence syn-

In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the

pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay pro-

grammed in the control register.

The ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface.

There are two timing reference signals, one at the beginning of each video data block SAV

(0xFF000080) and one at the end of each video data block EAV(0xFF00009D). Only data sent

between EAV and SAV is captured. Horizontal blanking and vertical blanking are ignored. Use of

the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the

interface, thereby reducing the pin count. In order to retrieve both frame and line synchronization

properly, at least one line of vertical blanking is mandatory.

相關(guān)PDF資料	PDF描述
MT80C31-25R	8-BIT, 25 MHz, MICROCONTROLLER, PQFP44
MQ80C52TXXX-16/883	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
MR80C52EXXX-20SCD	8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44
MR80C32-16SHXXX	8-BIT, 16 MHz, MICROCONTROLLER, CQCC44
MD80C32EXXX-30/883	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
MQ82370-20	制造商:Rochester Electronics LLC 功能描述:- Bulk
MQ8238020	制造商:Intel 功能描述:CONTROLLER: OTHER
MQ82380-20	制造商:Rochester Electronics LLC 功能描述:- Bulk
MQ82380-20/R	制造商:Rochester Electronics LLC 功能描述:
MQ82592	制造商:Rochester Electronics LLC 功能描述:- Bulk

發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

(若只采購一條型號，填寫一行即可)

*型號	*數(shù)量	廠商	批號	封裝