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型號(hào)：	MQ80C52CXXX-36SBR
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	1220/1447頁(yè)
文件大小：	3788K
代理商：	MQ80C52CXXX-36SBR

6437E–ATARM–23-Apr-13

37.11 HSMCI Boot Operation Mode

In boot operation mode, the processor can read boot data from the slave (MMC device) by keep-

ing the CMD line low after power-on before issuing CMD1. The data can be read from either the

boot area or user area, depending on register setting.

Boot Procedure, Processor Mode

Configure the HSMCI data bus width programming SDCBUS Field in the

HSMCI_SDCR register. The BOOT_BUS_WIDTH field located in the device Extended

CSD register must be set accordingly.

Set the byte count to 512 bytes and the block count to the desired number of blocks,

writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.

Issue the Boot Operation Request command by writing to the HSMCI_CMDR register

with SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data

The BOOT_ACK field located in the HSMCI_CMDR register must be set to one, if the

BOOT_ACK field of the MMC device located in the Extended CSD register is set to one.

Host processor can copy boot data sequentially as soon as the RXRDY flag is

When Data transfer is completed, host processor shall terminate the boot stream by

writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.

Boot Procedure, DMA Mode

Configure the HSMCI data bus width by programming SDCBUS Field in the

HSMCI_SDCR register. The BOOT_BUS_WIDTH field in the device Extended CSD

Set the byte count to 512 bytes and the block count to the desired number of blocks by

writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.

Enable DMA transfer in the HSMCI_DMA register.

Configure DMA controller, program the total amount of data to be transferred and

enable the relevant channel.

Issue the Boot Operation Request command by writing to the HSMCI_CMDR register

with SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data

DMA controller copies the boot partition to the memory.

When DMA transfer is completed, host processor shall terminate the boot stream by

writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.

37.12 HSMCI Transfer Done Timings

Definition

The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is

Read Access

During a read access, the XFRDONE flag behaves as shown in Figure 37-11.

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MQ82380-20	制造商:Rochester Electronics LLC 功能描述:- Bulk
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